3D Semiconductor Metal Layer Structure for Annealing Heat Shielding

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Solution Overview

Problem

Existing 3D stacked integrated circuits face challenges in heat removal due to high power density and thermal resistance, with conventional heat removal methods like liquid coolant and thermal vias being inefficient, and high-temperature processing damaging underlying metallization and device layers.

Innovation Solution

Incorporating a heat spreading and conducting material layer between sensitive metal interconnect layers and the annealing source to prevent damage during high-temperature processing, and using a shield to manage heat distribution in 3D-IC structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high-temperature processing is used to anneal crystalline silicon layers, then crystal quality is improved, but underlying metal interconnect layers are damaged

Engineering Contradiction:
Improvecrystal qualityVSAvoiddamage to metal interconnects
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A sacrificial metal layer is introduced as an intermediary between the annealing source and the sensitive metal interconnect layers. This sacrificial layer absorbs the thermal energy during annealing processes, preventing direct thermal damage to the underlying metal interconnects while still allowing sufficient heat to reach the crystalline silicon layer for quality improvement

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial metal layer is deposited beforehand on the metal interconnect layers before the crystalline silicon layer is annealed. This preliminary placement of the protective layer ensures that when high-temperature annealing is subsequently performed, the protection is already in place, preventing thermal damage to the metal interconnects

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If conventional heat removal methods (liquid coolant, thermal vias) are used in 3D stacked ICs, then heat management is attempted, but efficiency is insufficient due to high power density and thermal resistance

Engineering Contradiction:
Improveheat removal efficiencyVSAvoiddevice performance under high power density
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The metal interconnect layers themselves are designed to serve dual functions: electrical interconnection and heat dissipation. By utilizing the inherent thermal conductivity of the metal interconnect structure, the system removes heat through its own existing pathways without requiring additional dedicated cooling infrastructure, thereby improving heat removal efficiency while maintaining device reliability

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively manages heat distribution and prevents damage to underlying metal interconnects during high-temperature processing, enhancing the reliability and performance of 3D-IC devices.

Implementation Method 1

a first metal layer... a second metal layer... a third metal layer... wherein the first metal layer, the second metal layer, and the third metal layer have been heated to a first temperature that is greater than a melting point of a metal interlayer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

the first crystalline silicon layer and the second crystalline silicon layer have been annealed at a second temperature

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS12400961B23D semiconductor device and structure with metal layers
Publication Date: 2025.08.26 MONOLITHIC 3D INC
  • US12400961B2 patent drawing
  • US12400961B2 patent drawing
  • US12400961B2 patent drawing

AI summary

A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.