3D Semiconductor Metal Layer Structure for Low-Thermal-Resistance Stacking
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Solution Overview
Problem
In 3D stacked integrated circuits, the degradation of wire performance with 'scaling' leads to increased thermal resistance and heat removal challenges, particularly due to high thermal resistance in heat-producing regions and the damage caused by hydrogen ion implantation methods used in lattice structure formation.
Innovation Solution
The implementation of a hybrid bonding method with a shield/heat sink layer that incorporates high thermal conductivity materials like tungsten and copper, combined with optical annealing for defect repair and dopant activation, to form defect-free single crystalline semiconductor layers at low temperatures, thereby improving heat dissipation and reducing damage to underlying devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hydrogen ion implantation is used to form lattice structure, then single crystal silicon layers can be formed, but thermal resistance increases and heat removal becomes difficult
Solution Approach 1:
The patent introduces a shield/heat sink layer as an intermediary component between the hydrogen ion implantation region and the underlying devices. This layer serves dual purposes: protecting underlying structures from damage while providing a thermal conduction path to remove heat generated during the implantation process, thereby resolving the contradiction between achieving high-quality lattice structure and managing thermal resistance.
Solution Approach 2:
The patent replaces conventional high-temperature thermal annealing with optical annealing methods. By using light energy instead of thermal energy to repair lattice defects and activate dopants, the process avoids generating excessive heat that would increase thermal resistance and damage underlying devices, while still achieving the desired lattice structure quality.
2Reliability
If conventional high temperature annealing is used for defect repair, then lattice defects can be corrected, but metal interconnect layers are damaged
Solution Approach 1:
The patent substitutes thermal annealing with optical annealing using light sources such as lasers or LED arrays. This optical energy directly repairs lattice defects and activates dopants without generating the widespread thermal field that damages metal interconnect layers. The optical method provides localized, controlled energy delivery that corrects lattice issues while preserving the integrity of underlying metal structures.
Solution Approach 2:
The patent changes the fundamental parameter of energy delivery from thermal (high temperature) to optical (light energy). This parameter change allows defect repair to occur at effectively lower temperatures, preventing thermal damage to metal interconnect layers while maintaining the ability to correct lattice defects and activate dopants through photonic energy absorption by the silicon lattice.
3Productivity
If wire scaling is continued to improve transistor density, then transistor performance improves, but wire performance degrades and thermal resistance increases
Solution Approach 1:
The patent addresses wire scaling limitations by transitioning to three-dimensional integrated circuit architectures. Instead of continuing to scale wires in two dimensions (which increases thermal resistance), the invention stacks multiple device layers vertically in the third dimension. This dimensional change allows transistors to be placed closer together through vertical stacking rather than horizontal scaling, maintaining transistor density improvements while managing thermal resistance through the introduction of intermediate heat sink layers between stacked devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat removal efficiency by reducing thermal resistance and preventing damage to metal interconnect layers, allowing for the construction of 3D ICs with improved performance and reliability.
Implementation Method 1
a shield/heat sink layer that incorporates high thermal conductivity materials like tungsten and copper
Implementation Method 2
optical annealing for defect repair and dopant activation, to form defect-free single crystalline semiconductor layers at low temperatures
Implementation Method 3
optical annealing for defect repair and dopant activation
Implementation Method 4
The implementation of a hybrid bonding method with a shield/heat sink layer
Data Source
AI summary
A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.