3D Metal Line Layout for Stacked Gate-All-Around Transistors
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Solution Overview
Problem
As semiconductor technologies progress to smaller feature sizes, traditional two-dimensional (2D) circuit fabrication faces challenges in scaling, leading to a need for three-dimensional (3D) semiconductor circuits where transistors are stacked, requiring advanced methods for designing and forming 3D metal lines to enhance device performance.
Innovation Solution
The method involves forming a stack of alternating conductive and dielectric layers, creating openings to grow epitaxial semiconductor layers, and forming transistor channels that extend between metal layers, enabling a gate-all-around (GAA) structure for increased transistor density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-dimensional circuit fabrication is used, then manufacturing process is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar circuits to three-dimensional stacked circuits by forming multiple transistor layers vertically. Metal lines are designed to extend between stacked transistor layers, enabling vertical interconnects and significantly increasing device density within the same footprint area.
Solution Approach 2:
The fabrication process is segmented into distinct stages: forming alternating conductive and dielectric layers, creating openings, depositing semiconductor layers, and forming transistor channels. This segmentation allows complex 3D structures to be built systematically through repeated modular steps.
2Area of moving object
If feature sizes are reduced to scale down devices, then more transistors fit in planar area, but fabrication challenges increase significantly
Solution Approach 1:
Instead of continuing to scale down planar features, the patent utilizes the vertical dimension to accommodate more transistors. By stacking transistor layers and forming vertical metal line interconnects, the design achieves higher density without requiring further reduction of lateral feature sizes, thereby avoiding the escalating fabrication precision challenges.
3Productivity
If three-dimensional stacked transistor structures are formed, then device density increases, but metal line design and fabrication complexity increases
Solution Approach 1:
The metal line structure is segmented into portions extending between different stacked transistor layers. Each metal line portion is formed through a sequence of deposition and patterning steps, allowing complex 3D interconnects to be built from simpler modular segments rather than attempting to form complete structures in a single step.
Solution Approach 2:
Conductive and dielectric layers are formed in alternating sequences before transistor channels are fully defined. Openings are created through the layered structure prior to semiconductor layer deposition, enabling subsequent steps to proceed with pre-prepared templates and reducing overall fabrication complexity.
4Adaptability or versatility
If alternating conductive and dielectric layers are formed with openings, then vertical interconnects are enabled, but process steps increase
Solution Approach 1:
The alternating conductive and dielectric layer structure serves multiple functions: it provides mechanical support, defines interconnect pathways, enables vertical stacking, and facilitates heat dissipation. This multi-functional approach consolidates several requirements into a single structural solution, offsetting the increased number of process steps with greater overall efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher density circuits with improved transistor performance by allowing high electron and hole concentrations and self-aligned source/drain regions, facilitating efficient circuit layout and customization of N+S/D and P+S/D metal stacks, thus overcoming scaling limitations in planar devices.
Implementation Method 1
forming an opening in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening; forming a second stack of layers within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack
Data Source
AI summary
A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.