3D Metal Routing Layout for Dense Vertical Channel Integration
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in scaling transistors to single-digit nanometer nodes, where traditional 2D circuits face limitations in increasing transistor density, and transitioning to 3D integration for logic chips is complex, especially in achieving optimal metal routing path lengths for improved performance and speed.
Innovation Solution
The method involves forming a layer stack with alternating metal and dielectric layers, creating vertical channel structures through epitaxial growth, and optimizing metal routing by forming metal openings that allow for high-density routing and 90-degree angle metal formation, enabling higher device performance and speed through optimized path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D circuit scaling is used to increase transistor density, then transistor density per unit area increases, but scaling enters single digit nanometer nodes where greater challenges are experienced
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking, where transistors are arranged in multiple layers stacked vertically. This dimensional change allows continued scaling and density improvement without the severe constraints of single-digit nanometer 2D fabrication, effectively moving the problem from a two-dimensional scaling challenge to a three-dimensional integration solution.
2Quantity of substance
If 3D integration is implemented for logic chips, then transistor density in volume increases, but metal routing path length optimization becomes substantially more difficult
Solution Approach 1:
The patent segments the metal routing into multiple hierarchical layers (first metal layer, second metal layer, third metal layer) with distinct functions. Each layer handles specific routing tasks, allowing independent optimization of path lengths for different signal types and reducing overall routing complexity despite the 3D structure.
Solution Approach 2:
The patent utilizes the vertical dimension to create shorter routing paths by allowing metal connections to extend vertically between stacked transistor layers. This 3D routing capability reduces the horizontal distance signals must travel compared to traditional 2D layouts, optimizing performance in the vertical direction.
3Adaptability or versatility
If cap layer etching is performed in a contained area, then freedom to place contacts anywhere on the device is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs cap layer etching to create predefined opening patterns before subsequent metal deposition and contact formation steps. This preliminary action establishes the geometric constraints and available spaces for contact placement, allowing flexibility within the etched regions while maintaining manufacturing precision through controlled etch processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher device performance and speed by allowing for high-density routing and 3D metal integration around 90-degree angles, overcoming scaling limitations and enhancing transistor density in 3D semiconductor devices.
Implementation Method 1
Vertical channel structures are formed extending through a channel opening of the first layer stack including a vertical channel structure for each sub-stack, the vertical channel structures formed by epitaxial growth
Implementation Method 2
isotropically removing accessible portions of the first dielectric material through the metal openings
Data Source
AI summary
A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.