3D Semiconductor Metal Layer Stack for Dense Vertical Connectivity
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Solution Overview
Problem
The increasing cost of mask sets and limitations in vertical connectivity due to large Through-Silicon-Vias (TSVs) in 3D ICs pose challenges for reducing development costs and enhancing performance and power efficiency in semiconductor manufacturing, particularly for custom products targeting smaller markets.
Innovation Solution
The development of multilayer 3D ICs using single crystal transistors and advanced bonding techniques, such as oxide-to-oxide bonding and metal-to-metal bonding, along with reduced-size vias and multiple lithography steps, to enhance vertical connectivity and reduce reliance on TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through-Silicon-Vias (TSVs) are used for vertical connectivity in 3D ICs, then device density is improved, but TSV size increases causing connectivity limitations
Solution Approach 1:
The patent segments the vertical connectivity function by introducing multiple via types (contact vias, interlayer vias, through-layer vias) with different sizes and functions at different levels of the 3D IC structure, replacing the reliance on large TSVs for all connectivity needs
Solution Approach 2:
The patent transitions from relying solely on vertical TSV connectivity to incorporating horizontal metal interconnect layers that provide alternative routing paths, effectively adding a dimensional aspect to connectivity that reduces dependence on vertical via size
2Reliability
If advanced bonding techniques are implemented, then vertical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary bonding surface preparation and alignment procedures before the actual bonding process, ensuring that oxide-to-oxide and metal-to-metal bonding interfaces are properly prepared in advance to reduce manufacturing complexity during assembly
Solution Approach 2:
The patent uses oxide layers as intermediary bonding surfaces that facilitate reliable oxide-to-oxide bonding between stacked devices, while metal layers serve as intermediaries for metal-to-metal bonding, simplifying the direct bonding process
3Manufacturing precision
If multiple lithography steps are used, then manufacturing precision is improved, but development costs increase
Solution Approach 1:
The patent segments the lithography process into multiple steps, each targeting specific layers or features, allowing precise control over alignment for different structural elements while optimizing the overall process for cost-effectiveness
Solution Approach 2:
The patent changes lithography parameters (such as wavelength, numerical aperture, and exposure energy) across different lithography steps to achieve varying levels of precision for different features, optimizing the balance between manufacturing precision and development cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved vertical connectivity by an order of magnitude, reduces development costs, and enhances yield and reliability in complex 3D ICs, addressing the limitations of existing 3D IC technologies.
Implementation Method 1
bond regions comprising hybrid bonds, said bond regions are disposed between said first level and said second level
Implementation Method 2
bond regions comprising hybrid bonds
Data Source
AI summary
A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.