3D Semiconductor Metal Layer Stack for Dense Vertical Interconnects
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom products targeting smaller volume and less diverse markets, and the limitations in vertical connectivity due to the large size of Through-Silicon-Vias (TSVs) in 3D Integrated Circuit (IC) technology, which hinders performance and power enhancement.
Innovation Solution
The development of multilayer or Three Dimensional Integrated Circuit (3D IC) devices using single crystal transistors with oxide-to-oxide bonding and hybrid bonds, along with advanced layer transfer techniques such as SmartCut and ELTRAN, to reduce lithography steps and enhance vertical connectivity, allowing for more efficient interconnects and lower construction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through-Silicon-Vias (TSVs) are used for vertical connectivity in 3D ICs, then device density is improved, but the large size of TSVs limits vertical connectivity and hinders performance enhancement
Solution Approach 1:
The patent segments the vertical interconnect structure into multiple components: shallow TSVs for lower layers, deep TSVs for upper layers, and through-layer vias (TLVs) for intermediate connections. This segmentation allows each via type to be optimized for its specific function, reducing the overall size and improving vertical connectivity compared to using only large TSVs throughout the structure.
Solution Approach 2:
The patent introduces a new dimensional approach by creating intermediate connection layers between stacked devices. Instead of relying solely on vertical TSVs, the invention uses through-layer vias that extend partially through intermediate layers, effectively adding a horizontal dimension to the vertical interconnect architecture and enabling more flexible routing paths.
2Manufacturing precision
If multiple lithography steps are used for constructing 3D ICs, then manufacturing precision is improved, but development cost increases exponentially
Solution Approach 1:
The patent incorporates alignment marks and reference structures during the initial fabrication steps of each device layer. These preliminary features are built into the device structure itself, enabling subsequent layers to be aligned accurately without requiring additional dedicated lithography steps for alignment, thereby reducing overall manufacturing cost while maintaining precision.
Solution Approach 2:
The patent designs the interconnect structure so that the same lithography patterns serve multiple functions: defining both device features and alignment references, creating both functional interconnects and structural support elements. This multi-functionality reduces the total number of lithography steps required while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.