3D MIM Capacitor Layout for Multi-Value BEOL Capacitance
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Solution Overview
Problem
Current BEOL processing for semiconductor devices lacks flexibility in fabricating metal-insulator-metal (MIM) capacitors with varying capacitance values, limiting IC design options and requiring significant space for routing electrical conductors.
Innovation Solution
The fabrication of multiple MIM capacitors with different capacitance values, including 3D-MIM and shallow 3D-MIM capacitors, is achieved by forming deep and shallow trench capacitors within the BEOL processing stage, utilizing a MIM multilayer with high-k dielectric materials and conductive layers, and optimizing the cap structure for compact design and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional BEOL processing is used for MIM capacitor fabrication, then the process is simple, but the flexibility in fabricating capacitors with varying capacitance values is limited
Solution Approach 1:
The patent segments the capacitor fabrication process into distinct deep trench and shallow trench formation stages, allowing independent control of capacitance values. Different trench depths can be etched through selective masking and etching parameters, enabling multiple capacitance values from a single BEOL processing sequence without requiring entirely separate process flows.
Solution Approach 2:
The patent introduces depth as an additional dimension for capacitor design by forming trenches at different depths within the dielectric layers. This vertical dimensionality allows capacitance variation without increasing lateral footprint, enabling flexible capacitance scaling while maintaining compact device geometry and simplifying routing space requirements.
2Adaptability or versatility
If more space is allocated for MIM capacitor fabrication, then capacitor design options increase, but the available area for routing electrical conductors decreases
Solution Approach 1:
By utilizing the vertical dimension through deep and shallow trench formation, the patent enables multiple capacitor designs within a reduced lateral footprint. This allows routing conductors underneath and around capacitors with sufficient space, as the capacitance variation is achieved vertically rather than laterally.
Solution Approach 2:
The patent nests multiple capacitor structures (deep trench and shallow trench capacitors) within the same BEOL processing framework and overlapping lateral footprints. Different trench depths are formed through selective etching, allowing capacitors to be nested vertically within the dielectric stack, thereby conserving lateral space for conductor routing.
3Manufacturing precision
If deep trenches are etched through dielectric material, then 3D-MIM capacitors with high capacitance values are achieved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary patterning and masking steps before etching to precisely define trench locations and depths. By pre-configuring the dielectric stack with appropriate layer thicknesses and forming preliminary trenches, the subsequent etching process achieves high precision capacitance values while maintaining manufacturing simplicity through standardized process modules.
Solution Approach 2:
The patent applies local quality by using selective masking and etching parameters to create different trench depths in different regions. This allows precise control of capacitance values in specific locations without affecting other areas, achieving high manufacturing precision through localized process adjustment rather than global process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for greater flexibility in IC design by enabling the fabrication of capacitors with widely different capacitance values in a limited area, while also providing space for routing electrical conductors underneath the capacitors, enhancing the integration and functionality of semiconductor devices.
Implementation Method 1
a first dielectric material layer spaced apart from the patterned metallization layer and having a dielectric constant greater than a dielectric constant of the intermetal dielectric material
Data Source
AI summary
Fabricating a metal-insulator-metal (MIM) capacitor structure includes: forming a patterned metallization layer; disposing a dielectric material on the patterned metallization layer; etching one or more deep trenches through the dielectric material to the patterned metallization layer; depositing a MIM multilayer on the dielectric material and inside the one or more deep trenches formed in the dielectric material; and fabricating at least one three-dimensional MIM (3D-MIM) capacitor comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches; and fabricating at least one second capacitor, including at least one shallow 3D-MIM capacitor comprising a portion of the MIM multilayer deposited inside one or more shallow trenches passing partway through the dielectric material that are shallower than the one or more deep trenches, and/or at least one two-dimensional MIM (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material.