3D MIM Capacitor Structure for Higher Capacitance and Lower Leakage
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Solution Overview
Problem
The challenge in semiconductor integrated circuits is to increase capacitance per unit area in metal-insulator-metal (MIM) capacitors while minimizing damage to high-k dielectric materials and reducing leakage current, which is exacerbated by decreasing dimensions and etching processes.
Innovation Solution
The formation of MIM capacitors with larger top electrodes covering the dielectric layers to protect high-k dielectric materials from etching damage, combined with conformal deposition techniques to enhance uniformity and reduce non-uniformity defects, results in higher capacitance and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching processes are used to decrease geometry size, then functional density increases, but damage to high-k dielectric materials increases
Solution Approach 1:
The patent applies preliminary action by forming a protective cap electrode structure before the damaging etching processes occur. The cap electrode is deposited conformally over the high-k dielectric material, creating a protective layer that prevents etching damage to the dielectric while allowing subsequent geometry reduction through etching of other structures.
Solution Approach 2:
The cap electrode acts as an intermediary protective layer between the etching process and the high-k dielectric material. This intermediary structure absorbs the harmful effects of the etching process, preventing direct contact between the etchant and the sensitive dielectric material, thus enabling geometry reduction without dielectric damage.
2Ease of manufacture
If conventional MIM capacitor structures are used, then manufacturing is simpler, but capacitance per unit area is lower
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional structure with a cap electrode that covers the top and sidewalls of the underlying electrode. This dimensional change increases the effective capacitance per unit area by utilizing vertical space and sidewall surfaces, while the conformal deposition technique maintains manufacturing feasibility through standard semiconductor processes.
3Productivity
If dimensions are decreased to increase functional density, then more devices fit per chip area, but leakage current increases
Solution Approach 1:
The cap electrode serves as an intermediary barrier that prevents direct exposure of the high-k dielectric material to damaging etching processes. By protecting the dielectric interfaces from etching-induced defects and contamination, the cap electrode reduces leakage current pathways while enabling continued scaling to increase functional density.
Solution Approach 2:
The cap electrode is a sacrificial protective structure that is deposited, provides protection during critical processes, and can be selectively removed or integrated into the final device structure. This disposable protective element enables the manufacturing of smaller, higher-density capacitors with reduced leakage by protecting against process-induced damage throughout fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a higher capacitance per unit area, reduces dielectric layer damage, and improves the reliability of MIM capacitors by two orders of magnitude in leakage current reduction.
Implementation Method 1
conformal deposition techniques to enhance uniformity and reduce non-uniformity defects
Data Source
AI summary
The present disclosure relates to a semiconductor structure and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure. The MIM capacitor structure includes a first capacitor electrode formed on a top surface of a substrate, a dielectric layer formed on top and side surfaces of the first capacitor electrode and on the top surface of the substrate, and a second capacitor electrode formed on top and side surfaces of the dielectric layer. The first capacitor electrode has a first width. The second capacitor electrode has a second width greater than the first width.