3D MIM Capacitor Leakage Reduction via Polymer Layer Extraction
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Solution Overview
Problem
Traditional 3D MIM capacitors in semiconductor devices face challenges with increased leakage current, which reduces performance and requires additional processing steps and materials, limiting their efficiency and area utilization.
Innovation Solution
A method for forming a 3D MIM capacitor involves a substrate with a polymer dielectric layer, a redistribution layer with a metal layer, and a capacitive stack with a dielectric layer, where the dielectric layer is conformally deposited and etched to reduce leakage current without the need for additional polymer layers, enhancing performance and reducing processing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a 3D MIM capacitor is constructed to increase capacitance surface area, then area utilization is improved, but leakage current increases which reduces performance
Solution Approach 1:
The patent extracts and removes the problematic additional polymer dielectric layer that was causing leakage current issues in traditional 3D MIM capacitor structures. By taking out this unnecessary layer, the invention eliminates the source of leakage while preserving the high capacitance surface area benefits of the 3D structure.
Solution Approach 2:
The invention converts the harmful leakage current effect into a beneficial outcome by identifying that the additional polymer layer is the cause of leakage, and its removal resolves the issue. The harm (leakage) is converted into benefit (improved performance) through the insight that simplifying the structure eliminates the problem.
2Ease of manufacture
If additional polymer dielectric layers are added to the 3D MIM capacitor structure, then manufacturing complexity increases, but processing time and costs increase
Solution Approach 1:
The patent removes the additional polymer dielectric layer from the manufacturing process, thereby reducing the number of deposition and etching steps required. This extraction of unnecessary process steps directly reduces processing time and simplifies manufacturing while maintaining the desired capacitor functionality.
Solution Approach 2:
Instead of adding more layers to improve performance (the conventional approach), the invention inverts the strategy by removing layers to achieve better performance. This inversion reveals that the traditional multi-layer approach was overly complex and that simplification leads to both reduced processing time and improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 3D MIM capacitor with reduced leakage current, improved system performance, and faster processing times by minimizing the number of required layers, while maintaining efficient area utilization.
Implementation Method 1
depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer
Implementation Method 2
removing a portion of the dielectric layer to expose at least a portion of the top electrode
Data Source
AI summary
Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.