3D MIM Capacitor Fabrication with Orthogonal Electrodes
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Solution Overview
Problem
Existing integrated circuits with 3D MIM capacitors face challenges in achieving high capacity while maintaining integration density and reducing manufacturing defects, particularly due to copper-induced hillocks that affect electrical performance and surface area utilization.
Innovation Solution
A method involving the formation of trenches in an insulating layer with a MIM stack covering the walls and bottom, filled with metallic material like copper, which allows for orthogonal and parallel electrode sections, reducing defects and enhancing capacity without increasing surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If copper is deposited to form metallic layer 8, then the metallic interconnection level is formed, but copper-induced hillocks form on the surface causing manufacturing defects and reduced electrical performance
Solution Approach 1:
A planarization layer is formed over the copper-containing metallic layer 8 before subsequent processing steps. This preliminary planarization action prevents hillock formation from affecting later capacitor fabrication steps by flattening the surface early in the process sequence.
Solution Approach 2:
A planarization layer is introduced as an intermediary element between the copper metallic layer 8 and the capacitor structure. This intermediate layer isolates the hillock-prone copper layer from the capacitor fabrication process, allowing copper deposition without transferring surface defects to the capacitor electrodes.
2Area of stationary object
If 3D MIM capacitors are formed with vertical electrodes to reduce size, then integration density improves, but capacity is limited compared to capacitors with larger surface area
Solution Approach 1:
The capacitor structure transitions from purely vertical electrodes to a hybrid configuration with both vertical sections (for compactness) and horizontal sections (for increased capacity). The horizontal electrode sections extend within the planarization layer, adding effective capacitance area without increasing the projected footprint on the substrate.
Solution Approach 2:
The capacitor electrodes are nested within the planarization layer structure, with horizontal sections embedded in the planarization material. This nesting allows the capacitor to utilize the volume of the planarization layer for additional capacitance while maintaining a compact footprint.
3Productivity
If thin dielectric layers are used between horizontal metallic interconnection lines to increase integration density, then more interconnection levels can be packed, but manufacturing precision requirements increase
Solution Approach 1:
The planarization layer is formed preliminarily to flatten the surface created by copper deposition and subsequent processing. This preliminary planarization establishes a flat reference plane that enables precise deposition of thin dielectric layers with controlled thickness, meeting the stringent precision requirements for high-density interconnection.
Data Source
AI summary
A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.