3D MIM Capacitor Assembly With Pillar Topography for Higher Capacitance
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Solution Overview
Problem
The integration of large-area capacitors in interconnect structures of integrated circuit components faces challenges in achieving increased capacitance while maintaining capacitor quality, as high dielectric materials with thin layers can lead to leakage current and reduced breakdown voltage, and non-planar designs like 2.5D MIMcaps struggle with unwanted coupling effects and aspect ratio limitations.
Innovation Solution
A multilayer structure with a stack of at least three electrically conductive layers separated by dielectric layers, formed conformally on a topography defined by dielectric pillars, allowing for increased capacitance through controlled height differences and via connections, enabling multiple parallel capacitors and a continuous conductive layer to fill the remaining volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a thin layer of dielectric material with high dielectric constant is used to increase capacitance, then capacitance value increases, but capacitor quality decreases with increased leakage current and reduced breakdown voltage
Solution Approach 1:
The patent transitions from planar (2D) MIMcap structures to three-dimensional structures by introducing dielectric pillars that extend vertically from the bottom conductive layer. This vertical dimension allows the capacitor to achieve larger effective surface area without increasing the planar footprint, thereby increasing capacitance while maintaining acceptable dielectric layer thicknesses that preserve capacitor quality and reliability.
2Ease of manufacture
If planar MIMcap design is used, then manufacturing is simple, but available surface area is limited preventing large capacitance values
Solution Approach 1:
The invention introduces vertical dielectric pillars that create a three-dimensional capacitor structure. This allows the effective surface area to be increased by utilizing the vertical dimension rather than expanding the planar footprint, thereby achieving large capacitance values while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The capacitor structure embeds multiple functional elements within a compact volume: dielectric pillars are positioned within the capacitor structure, conductive layers are deposited conformally on the pillar surfaces, and via connections are integrated into the structure. This nesting approach maximizes the use of available space to achieve large effective surface area without increasing the overall device footprint.
3Quantity of substance
If 2.5D MIMcap with dielectric pillars is used to increase surface area, then capacitance increases, but unwanted coupling effects between MIMcap and substrate occur
Solution Approach 1:
The patent introduces a bottom conductive layer that serves as an intermediary between the dielectric pillars and the silicon substrate. This bottom conductive layer acts as a shielding layer that decouples the capacitor structure from the substrate, preventing unwanted coupling effects while allowing the dielectric pillars to extend vertically and increase the effective surface area for capacitance.
4Quantity of substance
If higher aspect ratio of dielectric pillars is used to increase capacitance, then capacitance increases, but manufacturing complexity and technical challenges increase
Solution Approach 1:
The patent optimizes the aspect ratio of the dielectric pillars by adjusting parameters such as pillar height, diameter, and spacing to achieve the desired capacitance value while maintaining manufacturability. The bottom conductive layer provides a platform that allows for controlled pillar dimensions, enabling increased capacitance through moderate aspect ratios rather than extreme values that would complicate manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance while decoupling the capacitor from the silicon substrate, improving capacitor quality and reliability by allowing for effective surface area expansion and controlled layer thicknesses, thus addressing the limitations of planar and 2.5D MIMcaps.
Implementation Method 1
dielectric layers which separate the conductive layers from each other
Implementation Method 2
The MIMcap's capacitance value can be defined based on the effective surface area and the ratio of the dielectric constant to the thickness of the dielectric
Implementation Method 3
The large area capacitor can generally be referred to as metal-insulator-metal capacitor ('MIMcap'). The MIMcap can be assembled with two layers of electrically conductive materials separated by a thin dielectric.
Data Source
AI summary
The disclosed technology is related to semiconductor components, including a multilayer structure with a plurality of MIM capacitors. The capacitors are realized as an assembly of capacitors in the form of a stack of at least three electrically conductive layers, separated by dielectric layers and formed conformally on a topography defined by a plurality of dielectric pillars distributed on a conductive bottom plate formed on a first level of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate ayers of the stack become available for contacting the layers by via connections.