3D MIM Capacitor Structure for High Density Semiconductor Devices
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase capacitor density per unit area in MIM capacitors while maintaining high performance, which is hindered by the limitations of two-dimensional device size.
Innovation Solution
A three-dimensional MIM capacitor structure is integrated, where multiple capacitors are stacked in a dielectric layer, allowing for increased density without expanding the device size, achieved by forming a series of conductive and dielectric layers with specific materials like titanium nitride, copper, and silicon nitride, and using etching and plating processes to create interconnected electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the lateral area of the capacitor is expanded to increase capacitor density, then the capacitor density per unit area is improved, but the device size must be enlarged which is limited by the integrated circuit device size
Solution Approach 1:
The patent transitions from a two-dimensional planar capacitor structure to a three-dimensional vertical capacitor structure. The capacitor electrodes are formed as vertical pillars extending through multiple dielectric layers, with the capacitor density increased by utilizing the vertical dimension (height) rather than expanding the lateral footprint. This allows multiple capacitor structures to be stacked vertically within the same planar area, dramatically increasing capacitor density per unit area without enlarging the device size.
Solution Approach 2:
The patent implements a nested structure where multiple dielectric layers and electrode structures are stacked vertically, with each capacitor unit containing concentric or nested electrode arrangements. The three-dimensional capacitor structure embeds multiple functional layers (first dielectric layer, second dielectric layer, conductive layers) within each other in the vertical dimension, creating a compact nested architecture that maximizes capacitor density within the available space.
2Quantity of substance
If multiple conductive and dielectric layers are stacked to form three-dimensional MIM capacitors, then the capacitor density per unit area is increased, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the capacitor structure into multiple discrete layers and units: first dielectric layer, second dielectric layer, multiple conductive layers (lower electrode layer, upper electrode layer), and intermediate dielectric layers. Each layer is formed through separate manufacturing steps, allowing for modular fabrication and control. The capacitor structure is segmented into repeating units that can be systematically manufactured, making the complex three-dimensional structure manageable through standardized segmentation.
Solution Approach 2:
The patent employs preliminary actions in the manufacturing process, including forming the first dielectric layer and first conductive metal structure before creating the second dielectric layer and capacitor structures. Through holes are pre-formed in the second dielectric layer before filling with conductive material to create the vertical electrode structures. These preliminary preparatory steps simplify subsequent manufacturing operations and enable the complex three-dimensional architecture to be built systematically.
Data Source
AI summary
The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.