3D MIM Capacitor Trenches for Higher Density and Breakdown Voltage
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Solution Overview
Problem
Conventional MIM capacitors face challenges such as high manufacturing costs, inefficient spatial density, and breakdown voltage issues due to hillocks, which are exacerbated by the need for additional mask layers and limited vertical thickness of the top electrode.
Innovation Solution
The development of three-dimensional MIM capacitors that can be built concurrently with interconnect structures without additional masks, utilizing a process that involves etching a trench in a dielectric layer and chemical mechanical polishing to create a 3D bottom electrode, followed by deposition of an insulator and top electrode, thereby improving spatial density and reducing hillocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MIM capacitors are built with additional mask layers to define the top electrode, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the top electrode definition with the existing interconnect patterning process. The same mask and etch steps used to define interconnect lines are also used to define the top electrode, eliminating the need for separate mask layers dedicated to capacitor electrode definition.
Solution Approach 2:
The interconnect patterning process is given multiple functions: it simultaneously defines both the interconnect lines and the top electrode of the MIM capacitor. This multi-functional approach reduces overall process complexity while maintaining manufacturing precision.
2Reliability
If the top electrode thickness is increased to reduce resistance, then electrical conductivity is improved, but the vertical space available for other layers is reduced
Solution Approach 1:
The patent transitions from a conventional planar top electrode to a three-dimensional structure where the top electrode extends vertically along the sidewalls of the capacitor. This dimensional change allows increased electrode surface area and reduced resistance without consuming additional vertical space between metal layers.
Solution Approach 2:
The top electrode is nested within the capacitor structure, with portions extending into the sidewall regions. This nesting approach maximizes the use of available space within the capacitor footprint while maintaining proper layer spacing.
3Ease of manufacture
If aluminum interconnect structures are used with hillocks, then ease of manufacture is improved, but breakdown voltage is reduced due to uncontrolled hillock formation
Solution Approach 1:
The patent removes the problematic hillocks from the aluminum interconnect structure by selectively removing material in the capacitor region. This extraction of harmful features eliminates the source of breakdown voltage issues while preserving the ease of manufacture of aluminum interconnects.
Solution Approach 2:
The process includes preliminary steps to prevent hillock formation or to remove them before capacitor fabrication. By taking preliminary anti-action against hillock formation, the patent prevents the harmful effect from manifesting while maintaining the benefits of aluminum interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of MIM capacitors with improved spatial density and breakdown voltage, reducing manufacturing costs and eliminating the need for additional mask layers, while ensuring a hillock-free surface for enhanced performance.
Implementation Method 1
a first chemical mechanical polishing (CMP) of the entire integrated circuit structure dishes and erodes electrode metal adjacent the trench
Implementation Method 2
etching a trench in a dielectric layer
Implementation Method 3
depositing a conformal metal in the via or contact hole, the tub, and the trench
Data Source
AI summary
A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.