3D MIM Capacitor Top-Plate Interconnect Without Via Masks
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Solution Overview
Problem
Connecting the top plate of three-dimensional metal-insulator-metal (3D MIM) capacitors to external circuitry is challenging due to their 3D structure, requiring additional fabrication steps and masks, which complicates the process and increases costs.
Innovation Solution
A method for forming a MIM capacitor with a top plate that allows direct metal interconnect landing, eliminating the need for an additional via mask by using a damascene metal layer that directly contacts the top plate, and incorporating a dielectric layer with trenches to facilitate this connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional MIM capacitor structure is used to increase capacitance density, then capacitance density is improved, but fabrication complexity increases due to additional via masks required to connect top plate to external circuitry
Solution Approach 1:
The patent merges the top plate connection function with the interconnect layer by allowing the interconnect layer to directly contact the top plate surface. This eliminates the need for separate via structures and additional via masks, combining what would have been separate fabrication steps into a unified process while maintaining high capacitance density through the 3D capacitor structure.
Solution Approach 2:
The patent transitions from a planar connection approach to a three-dimensional surface contact approach. Instead of using vertical vias to reach the top plate, the interconnect layer makes contact with the top plate's upper surface, utilizing the third dimension (vertical surface area) to enable direct connection and simplifying the fabrication process.
2Reliability
If additional via masks are used to connect top plate to external circuitry, then connectivity is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the connectivity function with the existing interconnect layer structure. The interconnect layer serves dual purposes: maintaining electrical continuity in the circuit and providing direct contact to the top plate. This eliminates the need for additional via masks and associated manufacturing steps, reducing production costs while ensuring reliable connectivity.
Solution Approach 2:
The patent extracts the connectivity function from the via mask process and assigns it to the interconnect layer. By removing the requirement for separate via masks, the design simplifies the manufacturing process and reduces costs while maintaining the essential connectivity between the top plate and external circuitry.
3Area of moving object
If pixel size is reduced to increase sensor resolution, then image quality is improved, but capacitance density becomes insufficient
Solution Approach 1:
The patent transitions from two-dimensional planar capacitors to three-dimensional structures with increased surface area. By utilizing vertical trenches and extended top plate surfaces, the capacitor achieves higher capacitance density within a smaller footprint, enabling reduced pixel sizes while maintaining sufficient capacitance for image sensor operation.
Solution Approach 2:
The patent implements a nested structure where the bottom plate forms trenches that extend vertically, and the top plate overlays these trenches. This nested arrangement maximizes the capacitor's effective surface area within a compact volume, achieving high capacitance density that enables smaller pixel dimensions without sacrificing electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables image sensors with smaller pixel sizes and higher capacitance density while reducing fabrication complexity and costs by eliminating the need for additional via masks.
Implementation Method 1
Each image sensor pixel receives incident photons, such as light, and converts the photons into electrical signals
Implementation Method 2
Each image sensor pixel may include a capacitor to store charge representing the sensor signals
Data Source
AI summary
A 3D metal-insulator-metal (MIM) capacitor for CMOS image sensors. A MIM capacitor includes a dielectric layer defining a plurality of trenches, and a bottom plate of conductive material overlying the dielectric layer and lining sides of the plurality of trenches. The MIM capacitor also includes a capacitor dielectric directly overlying the bottom plate and extending into the plurality of trenches, a top plate of conductive material directly overlying the capacitor dielectric, and a damascene metal layer overlying and directly contacting the top plate.