3D MIM Capacitor Assembly With Pillar Heights for Higher Capacitance
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Solution Overview
Problem
Existing multilayer interconnect structures in semiconductor chips face challenges in increasing the capacitance of MIMcaps due to limited surface area, leading to issues with leakage current and breakdown voltage, particularly in non-planar designs like 2.5D MIMcaps, which can cause unwanted coupling with the silicon substrate.
Innovation Solution
A capacitor assembly is developed with a stack of at least three conductive layers separated by dielectric layers, conformally formed on a topography defined by dielectric pillars, allowing for height differences between pillars to enable multiple parallel capacitors through controlled thicknesses of additional dielectric layers and via connections, thereby increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the effective surface area of MIMcap is increased to achieve higher capacitance values, then the capacitance increases, but the available surface area on the chip is limited
Solution Approach 1:
The patent transitions from planar (2D) MIMcap design to a three-dimensional structure by introducing dielectric pillars with varying heights. This vertical dimensionality change allows the capacitor to utilize the third dimension (height) in addition to the planar surface area, thereby achieving higher capacitance values without requiring additional chip surface area. The conformal deposition of conductive layers on the pillar topography creates multiple capacitive elements stacked vertically.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers and dielectric layers are conformally deposited around and between dielectric pillars of different heights. This creates a nested arrangement where smaller capacitive elements are embedded within the larger three-dimensional structure, maximizing the use of available space and increasing the effective capacitance density.
2Quantity of substance
If thin dielectric layers are used to achieve high capacitance values, then the capacitance increases, but the leakage current increases and breakdown voltage decreases
Solution Approach 1:
By transitioning to a three-dimensional structure with dielectric pillars, the patent increases the effective surface area perpendicular to the current flow path. This allows the use of thicker dielectric layers (improving reliability) while maintaining high capacitance through the increased effective area provided by the vertical pillar structure.
Solution Approach 2:
The patent segments the capacitor structure into multiple discrete dielectric pillars with varying heights, each contributing to the total capacitance. This segmentation allows the electric field to be distributed across multiple isolated regions, reducing stress on any single dielectric layer and improving overall reliability while maintaining high total capacitance.
3Quantity of substance
If non-planar MIMcap structures like 2.5D pillars are used to increase surface area, then the capacitance increases, but unwanted coupling effects with the silicon substrate occur
Solution Approach 1:
The patent extracts the capacitor structure from direct contact with the silicon substrate by introducing an intermediate dielectric layer between the bottom conductive plate and the substrate. This isolation layer eliminates unwanted coupling effects and parasitic interactions between the capacitor and substrate while preserving the beneficial three-dimensional pillar structure for increased capacitance.
4Quantity of substance
If the aspect ratio of dielectric pillars is increased to further increase capacitance in 2.5D design, then the capacitance increases, but manufacturing challenges arise
Solution Approach 1:
The patent introduces variability in pillar heights as a dynamic design parameter, allowing optimization of each pillar's height according to its specific location and function within the capacitor assembly. This dynamic approach enables manufacturing within standard process capabilities while achieving high capacitance through the cumulative effect of multiple pillars with optimized individual dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances capacitance by enabling multiple parallel capacitors, improving the overall assembly's performance without compromising reliability or increasing leakage current.
Implementation Method 1
a stack of at least three electrically conductive layers, including a bottom layer, a top layer and at least one intermediate layer, wherein the stack further comprises dielectric layers which separate the conductive layers from each other
Data Source
Figure 1a~1c
Figure 2a~2c
Figure 3a~3e
AI summary
The invention is related to semiconductor components such as integrated circuit chips, comprising a multilayer structure such as a back end of line portion, with a plurality of MIM capacitors integrated between two levels of the multilayer structure. The capacitors are realized as an assembly of capacitors, in the form of a stack of at least three electrically conductive layers (20,21,22;50-53) , separated by dielectric layers (23,24,54-56), and formed conformally on a topography defined by a plurality of dielectric pillars (13) distributed on a bottom conductive plate (10) formed on a first level (Mn) of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate conductive layers of the stack become available for contacting said layers by via connections (5,8,35,60-63,70-72) of the next level of the interconnect structure. In this way, a circuit comprising multiple parallel capacitors can be realized, which significantly increases the capacitance of the overall assembly. The method of the invention includes the deposition of a thick dielectric layer (11a) and one or more additional dielectric layers (11a,11b, 11c, 11d) thereon. Openings (30,40,41) are produced in the additional layers before patterning the layers to form the pillars, so that the thicknesses of the additional layers determine the height differences between the pillars. By carefully controlling said thicknesses in relation to the thicknesses of the layers of the capacitor assembly, contacting of the intermediate conductive layers of the stack is enabled.