3D Metal-Insulator-Metal Capacitor with High Aspect Ratio Trenches
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Solution Overview
Problem
Conventional planar dual-electrode or triple-electrode metal-insulator-metal capacitors struggle to achieve high capacitance density, and existing 3D MIMCAP structures are costly to manufacture and not easily integrated into current process flows, hindering the development of smaller, more energy-efficient IoT devices.
Innovation Solution
Incorporating a 3D metal-insulator-metal capacitor with high aspect ratio trenches into the back-end-of-the-line metal levels, using stacked conformal layers of metal and insulator, and integrating dual-damascene processing to minimize costs and enhance capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar dual-electrode or triple-electrode metal-insulator-metal capacitors are used, then the manufacturing process is simple and well-integrated into current process flows, but the capacitance density is insufficient to achieve high values (approaching approximately 100 fF/μm2 or higher)
Solution Approach 1:
The patent transitions from conventional planar (2D) capacitor structures to three-dimensional (3D) structures by forming high aspect ratio trenches that extend vertically through multiple dielectric layers. This dimensional change allows the capacitor electrodes to occupy vertical space, dramatically increasing the effective capacitance area per unit chip surface area and achieving capacitance densities approaching or exceeding 100 fF/μm2.
Solution Approach 2:
The patent implements a nested structure where conformal metal and insulator layers are deposited sequentially to line the high aspect ratio trenches, creating a metal-insulator-metal stack nested within the trench geometry. This nested arrangement maximizes the use of vertical space within the trench, allowing multiple functional layers to be packed into a compact volume while maintaining the high capacitance density.
2Quantity of substance
If three-dimensional (3D) MIMCAP structures are developed to provide increased capacitance density, then the capacitance density increases, but the manufacturing techniques are not readily integrated into current process flows and may be deemed cost-prohibitive
Solution Approach 1:
The patent employs dual-damascene processing techniques that are already established in current semiconductor manufacturing for forming interconnect structures. By adapting these existing multi-functional processes to also form the capacitor structures, the patent enables seamless integration into current process flows without requiring entirely new manufacturing equipment or techniques, thereby reducing implementation costs and complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the high aspect ratio trenches and depositing the conformal metal-insulator-metal stacks during the back-end-of-line (BEOL) processing stages, specifically utilizing the UTM-level dual-damascene processing window. This timing allows the capacitor structures to be formed alongside other necessary interconnect structures, maximizing process integration and minimizing additional manufacturing steps.
3Quantity of substance
If high aspect ratio trenches are formed to increase capacitance density, then the capacitance per chip surface area increases, but the aspect ratio of the trenches increases making fabrication more challenging
Solution Approach 1:
The patent achieves high capacitance density by optimizing the aspect ratio parameter of the trenches, forming trenches with heights significantly greater than their widths (e.g., extending through multiple dielectric layers with thicknesses of 50-200 nm each). By carefully controlling this aspect ratio parameter and the corresponding trench dimensions, the patent maximizes the vertical capacitance contribution while remaining within the capabilities of existing lithography and etching processes.
Solution Approach 2:
The patent replaces mechanical drilling or punching methods with advanced lithography and anisotropic etching processes to form the high aspect ratio trenches. This substitution allows for precise control of trench geometry, including depth, width, and sidewall verticality, enabling the formation of high aspect ratio structures (aspect ratios of 5:1 or higher) with the required manufacturing precision.
Data Source
AI summary
Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures. Also disclosed are method embodiments for forming IC structures with such a MIMCAP and these method embodiments can be readily integrated into current BEOL processing, including UTM-level dual-damascene processing.