3D mmWave IC Stacking for Compact High-Power RF Integration
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Solution Overview
Problem
Existing technologies face challenges with high cost and integration of large dimensions and integration density, and integration flexibility, which can be improved specific application of high costs and integration flexibility, which can be improved specific application of high power amplification, voltage switching, and overall circuit efficiency.
Innovation Solution
A 3D-millimeter wave integrated circuit (3D-mmWIC) architecture that integrates silicon-based complementary metal-oxide semiconductor (Si CMOS) technology with gallium nitride (GaN) and other semiconductor materials, utilizing a substrate layer of silicon, dielectric layers, metal regions, and oxide layers to enhance RF circuit functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional monolithic GaN MMIC process is used, then high-power amplification capability is achieved, but the chip size becomes large and manufacturing cost increases
Solution Approach 1:
The patent segments the integrated circuit into two distinct substrates: a first substrate containing GaN high-electron-mobility transistors (HEMTs) for power amplification, and a second substrate containing Si CMOS circuitry for control and signal processing. This segmentation allows each substrate to be optimized independently, enabling high power capability in a compact form factor by placing only the essential power amplification components on the first substrate.
Solution Approach 2:
The patent transitions from a planar monolithic integration approach to a three-dimensional stacked architecture. By bonding the second substrate (Si CMOS) to the first substrate (GaN HEMTs) in the vertical dimension, the design achieves high integration density while maintaining compact chip footprint. This vertical stacking enables complex circuit functionality without increasing lateral chip size.
2Power
If a conventional monolithic GaN MMIC process is used, then high-power amplification is achieved, but manufacturing cost increases
Solution Approach 1:
The patent divides the manufacturing process into separate fabrication steps for the first substrate (GaN HEMTs) and second substrate (Si CMOS), allowing each to be manufactured using optimized processes for their respective materials. This segmentation enables the use of mature, cost-effective Si CMOS fabrication for the majority of circuit components while reserving expensive GaN processing only for the essential power amplification devices.
Solution Approach 2:
The second substrate utilizing Si CMOS technology serves multiple functions: it provides control circuitry, signal processing, impedance matching, and interconnect functionality. This multi-functionality reduces the need for additional GaN components, thereby reducing overall manufacturing cost while maintaining high-power amplification capability through the GaN HEMTs on the first substrate.
3Device complexity
If a conventional monolithic approach is used, then integration is achieved, but integration flexibility and design freedom are reduced
Solution Approach 1:
The patent segments the integrated circuit into independently designable and manufacturable substrates, allowing different material systems (GaN and Si) to be optimized for their specific functions. This segmentation provides design flexibility by enabling independent optimization of power amplification circuits on GaN and control/signal processing circuits on Si, while achieving high integration through substrate bonding.
Solution Approach 2:
The patent introduces an intermediary bonding interface between the first substrate (GaN HEMTs) and second substrate (Si CMOS) that enables flexible interconnection. This intermediary layer allows for various bonding configurations and interconnect schemes, providing design freedom in how the two substrate technologies are integrated while maintaining high integration density.
Data Source
AI summary
Aspects of the present disclosure relate to a 3D-millimeter wave integrated circuit (3D-mmWIC configured to improve the efficiency and functionality of radio-frequency (RF) circuits through a multi-material, multi-layered architecture. These aspects can integrate silicon-based complementary metal-oxide semiconductor (CMOS) technology with other semiconductor materials, including Gallium Nitride (GaN), graphene, and/or various semiconductor alloys from the periodic table's Groups II-VI and/or III-V. The 3D-mmWIC can employ a layered structure comprising a silicon substrate, interleaved dielectric layers with embedded metal regions of varying thicknesses and lengths, a semiconductor layer, and/or additional oxide and dielectric layers. This architecture can enable the integration of multiple source, drain, and gate modules, interconnected via a sophisticated metal/oxide network. The disclosed integrated circuit architecture can provide significant advancements in RF circuit integration, offering reductions in size and cost while increasing design flexibility and performance.