3D Electro-Optic Modulator Layout for Low-Capacitance Footprints

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Solution Overview

Problem

Existing optical modulators face challenges in achieving a smaller device footprint with lower capacitance and poly silicon induced scattering losses while maintaining high modulation efficiency and breakdown voltage.

Innovation Solution

The photonic electro-optical modulator is designed with interleaved portions of N+ and P+ regions, utilizing a three-dimensional overlap of carrier accumulation regions and optical fields, and employing a gate oxide that suppresses slot waveguide effects, resulting in a smaller footprint and improved field confinement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If traditional optical modulator designs are used, then device footprint is larger, but modulation efficiency and breakdown voltage are maintained

Engineering Contradiction:

Improvedevice footprintVSAvoidbreakdown voltage

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar 2D modulator design to 3D vertical stacking architecture. Multiple functional layers (optical waveguides, electrode structures, photodetectors) are stacked vertically to achieve higher integration density and reduced footprint while maintaining electrical performance through optimized vertical field confinement

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested functional structures where electrode patterns are embedded within optical waveguide layers, and multiple device functions (modulation, detection, signal routing) are integrated within a single stacked structure, reducing the overall device footprint

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If device footprint is reduced, then capacitance decreases, but poly silicon induced scattering losses increase

Engineering Contradiction:

Improvedevice footprintVSAvoidscattering losses

Core Design Contradiction:

Area of stationary objectVSLoss of energy

Solution Approach 1:

The patent changes the material parameter from poly silicon to single crystal silicon for waveguide fabrication. This material substitution reduces optical scattering losses while maintaining the reduced footprint benefits, as single crystal silicon has superior optical properties with minimal scattering

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures combining single crystal silicon waveguides with carefully engineered dielectric layers and metal electrodes. This composite approach optimizes both optical performance (minimizing scattering) and electrical performance (maintaining low capacitance) in the compact footprint

Inventive Principle:

Principle #40Composite materials

3Reliability

If three-dimensional overlap of carrier accumulation regions is implemented, then modulation efficiency increases, but device complexity increases

Engineering Contradiction:

Improvemodulation efficiencyVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent achieves three-dimensional carrier accumulation by stacking electrode layers vertically above and below optical waveguide modes. This vertical stacking creates overlapping electric fields that enhance modulation efficiency without requiring complex lateral patterning, thus managing device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Reliability

If gate oxide is used to suppress slot waveguide effects, then field confinement improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvefield confinementVSAvoidmanufacturing precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent optimizes the gate oxide layer thickness and material composition parameters to achieve effective field confinement. By carefully controlling these material parameters, the design suppresses slot waveguide effects while using standard semiconductor fabrication processes that can meet the precision requirements

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves lower capacitance, minimizes scattering losses, and enhances modulation efficiency without compromising breakdown voltage, allowing for high-speed operation at lower driving voltages.

Implementation Method 1

employing a gate oxide that suppresses slot waveguide effects, resulting in a smaller footprint and improved field confinement

Methodology Applied

Scientific EffectSlot waveguide effect suppression: Waveguide (optics)

Implementation Method 2

interleaved portions of N+ and P+ regions, utilizing a three-dimensional overlap of carrier accumulation regions and optical fields

Methodology Applied

Scientific EffectCarrier accumulation: Electrical Accumulator

Implementation Method 3

achieving a smaller device footprint with lower capacitance and poly silicon induced scattering losses

Methodology Applied

Scientific EffectPoly silicon induced scattering: Scattering

Data Source

PatentUS20250347938A1Optical devices and methods of manufacture

Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An optical device and method of manufacture is presented. In embodiments a method includes forming a first layer of optical material, patterning the first layer into a stair-step pattern, depositing a dielectric material onto the stair-step pattern, and forming a second layer of optical material over the dielectric material and at least partially within the stair-step pattern.