3D Semiconductor Module Stacking for Higher Capacity, Lower Thickness
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Solution Overview
Problem
Conventional semiconductor modules face limitations in achieving a large capacity and high performance due to miniaturization, susceptibility to noise, and increased chip area, while three-dimensional stacking techniques are needed to enhance data communication between chips.
Innovation Solution
A method for manufacturing a semiconductor module involving a first chip disposing step, redistribution layer forming, second chip disposing, pillar forming, and substrate disposing, with specific steps performed in varying orders to achieve a reduced thickness and low-cost production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacking technique is used to increase capacity, then memory capacity is improved, but module thickness increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar two-dimensional chip arrangement to three-dimensional stacking architecture. Multiple memory chips are stacked vertically along the thickness direction with redistribution layers and connection structures enabling electrical connections between stacked chips, thereby increasing storage capacity while maintaining a compact form factor.
Solution Approach 2:
The patent implements nesting by placing multiple functional layers within the vertical stack: memory chips are nested between redistribution layers, which are in turn nested between connection structures. This nested arrangement allows multiple chips to be integrated in a compact vertical space, increasing capacity without proportionally increasing module thickness.
2Speed
If high-speed data communication between chips is implemented, then communication speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming redistribution layers on the memory chips before stacking. These redistribution layers are prepared in advance with appropriate pad configurations to enable high-speed data communication interfaces. This preliminary preparation simplifies the overall manufacturing process by allowing standardized stacking procedures while maintaining high communication speeds between chips.
Data Source
AI summary
A method for manufacturing a semiconductor module that includes a plurality of chips includes a first chip arrangement step for arranging a first chip; a rewiring layer formation step for forming a rewiring layer that is disposed on one surface side of the first chip and that is electrically connected to a second chip; a second chip arrangement step for arranging the second chip on the other surface side of the rewiring layer, the other surface side being opposite to the rewiring layer surface facing the first chip, at a position overlapping the first chip in the opposing direction; a pillar formation step for forming a pillar that extends from the other surface of the rewiring layer; and a substrate arrangement step for arranging a substrate that is electrically connected to the pillar and the second chip.