3D Electronic Module Vertical Interconnection via Drilled Vias
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Solution Overview
Problem
The existing methods for fabricating 3D electronic modules are limited by the number of electrical connections between wafer levels due to the limited area of the lateral faces, and there is a need for a process that increases these connections while also allowing for collective fabrication to reduce costs.
Innovation Solution
The process involves creating vias within the electronic module stack to reduce the pitch of conductors, which includes fabricating wafer levels with geometric features, stacking, drilling vias through the resin, metallizing the via walls, and cutting along dicing lines to increase the number of connections between wafer levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductors are placed on lateral faces of the stack, then electrical connections are established between wafer levels, but the number of connections is limited by the area of the lateral face
Solution Approach 1:
The invention transitions from placing conductors only on the lateral faces (2D surface) to creating vias through the entire thickness of the stack (3D volume). By drilling vias vertically through multiple wafer levels and filling them with conductive material, the patent enables electrical connections in the vertical dimension, dramatically increasing the number of possible connections beyond what the lateral face area would allow.
Solution Approach 2:
The invention segments the connection path into multiple sections: horizontal tracks on individual wafer levels, vertical vias through the stack, and additional horizontal tracks on upper levels. This segmentation allows conductors to be distributed throughout the 3D structure rather than confined to a single lateral surface, enabling more connections to be packed into the available volume.
2Ease of manufacture
If conductors are spaced apart by a pitch of 200 μm, then manufacturing is simplified, but the number of conductors per lateral face area is reduced
Solution Approach 1:
By moving from 2D lateral face placement to 3D via-based placement, the invention exploits the vertical dimension to increase conductor density. The via approach allows multiple conductors to be stacked vertically through the same lateral footprint, effectively multiplying the number of connections without reducing the lateral pitch spacing.
3Productivity
If 3D modules are fabricated collectively, then production cost is reduced, but the process complexity increases
Solution Approach 1:
The invention merges multiple fabrication operations into a collective process: wafer-level fabrication of multiple modules simultaneously, stacking of complete wafer stacks, batch drilling of vias through entire stacks, and bulk metallization of all vias at once. This consolidation of operations achieves cost-effective collective fabrication while the modular via structure actually simplifies control compared to individual module processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the number of electrical connections between wafer levels, enabling more efficient vertical interconnection and reducing the cost of 3D module fabrication by allowing for collective production.
Implementation Method 1
metallizing the wall of the vias by electrolytic growth
Data Source
AI summary
A process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.