3D Monolithic LDMOS Transistor Vertical Drain
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Solution Overview
Problem
Conventional transistor designs occupy significant lateral area on substrates, limiting the density of transistor arrangements and the integration of additional devices.
Innovation Solution
A three-dimensional monolithic LDMOS transistor is fabricated with a vertically disposed drain structure, utilizing fully depleted silicon on insulator (FDSOI) technology and a voltage attenuation structure to reduce lateral area consumption, allowing for higher voltage operation without increasing the substrate footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor designs are used, then the transistor structure is simple and easy to manufacture, but the lateral area occupied is significant, limiting transistor density
Solution Approach 1:
The patent applies dimensionality change by transitioning from a conventional planar transistor layout to a three-dimensional vertical structure. The drain structure is positioned vertically above the gate and channel, utilizing the third dimension (height) to reduce the lateral footprint on the substrate. This vertical integration allows higher transistor density without increasing the substrate area occupied by each transistor.
2Power
If higher voltage operation is enabled, then the transistor performance is improved, but the lateral area increases
Solution Approach 1:
The patent resolves this contradiction by implementing a vertical drain structure that extends upward from the substrate. This three-dimensional configuration allows the transistor to support higher voltage operations through increased breakdown voltage capability provided by the vertical junction, while simultaneously reducing the lateral footprint compared to conventional planar designs that would require larger areas to achieve the same voltage handling capability.
Data Source
AI summary
A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.