3D MOS Transistor Structure With Doped Layer for Lower Resistance
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Solution Overview
Problem
Conventional planar MOS transistors face challenges in scaling down due to limitations in reducing transistor dimensions and improving performance, necessitating the development of stereoscopic or non-planar transistor technologies.
Innovation Solution
A doped semiconductor layer is introduced between a source structure and a semiconductor structure to reduce connection and channel resistances, enhancing the operation performance of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar MOS transistor is used, then manufacturing process is simple, but transistor dimension cannot be reduced and performance cannot be improved
Solution Approach 1:
The patent transitions from planar 2D transistor structure to a 3D stereoscopic structure by introducing a doped semiconductor layer between the source structure and channel structure, enabling vertical current flow in addition to horizontal flow. This dimensional change allows continued scaling while maintaining performance.
Solution Approach 2:
The transistor structure is segmented into distinct functional regions: source structure, doped semiconductor layer, channel structure, and drain structure. This segmentation allows independent optimization of each region's properties to achieve both small dimensions and high performance.
2Length of moving object
If transistor dimension is reduced, then device size decreases, but connection resistance and channel resistance increase
Solution Approach 1:
A doped semiconductor layer is introduced as an intermediary between the source structure and channel structure. This intermediate layer serves as a transition region that facilitates charge carrier flow, reducing connection resistance and improving overall device reliability despite miniaturization.
Solution Approach 2:
The doping concentration and electrical properties of the semiconductor layer are optimized to achieve low resistance. By controlling doping parameters, the layer provides excellent electrical contact between source and channel while maintaining the reduced dimension structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped semiconductor layer reduces resistance, thereby improving the operational performance of the semiconductor device by minimizing connection and channel resistances.
Implementation Method 1
A doped semiconductor layer is disposed between a source structure and a semiconductor structure for improving operation performance of the semiconductor device
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are in the present invention. The semiconductor device includes a substrate, a source structure, a semiconductor structure, a gate structure, and a doped semiconductor layer. The source structure is disposed on the substrate. The semiconductor structure is disposed above the source structure. The gate structure is disposed above the source structure and surrounds the semiconductor structure. The doped semiconductor layer is disposed between the source structure and the semiconductor structure. Accordingly, the operation performance of the semiconductor device may be improved.