3D MOSFET Channel Structure for Source/Drain Connection Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring vertically stacked channel patterns, source/drain patterns, gate electrodes, and spacers, with specific spacer configurations and manufacturing processes to enhance connectivity and reliability, including ion implantation and etching techniques to form recesses and spacers, thereby improving the connection distribution between source/drain and channel patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D channel patterns, enabling multiple channels to occupy a smaller footprint area while maintaining improved electrical characteristics and operational reliability through enhanced channel control
Solution Approach 2:
The channel region is divided into multiple discrete channel patterns stacked vertically, with each channel providing independent current flow paths. This segmentation allows better electrical characteristics while occupying reduced planar area
2Length of moving object
If spacer width is reduced to accommodate smaller device dimensions, then device miniaturization is achieved, but connection distribution between source/drain and channel patterns deteriorates
Solution Approach 1:
The spacer structure extends in the vertical dimension with controlled width at different levels. The first width at the upper surface level ensures proper connection distribution, while the second width at lower levels accommodates miniaturization requirements, resolving the contradiction through dimensional variation
Solution Approach 2:
Different portions of the spacer have different widths tailored to local requirements: the upper portion maintains larger width for optimal source/drain to channel connection distribution, while lower portions are narrower to achieve overall device miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the electrical characteristics and reliability of semiconductor devices by optimizing the connection distribution between source/drain and channel patterns, enhancing the device's performance and operational stability.
Implementation Method 1
performing an ion implantation process after forming an inner spacer layer conformally covering inner walls of the mask recesses
Implementation Method 2
etching the stacked pattern using the hard mask patterns, the inner spacers, and the outer spacers as an etch mask to form a recess
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a pair of channel patterns spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns, a source/drain pattern between the pair of channel patterns, a pair of gate electrodes on the channel patterns, an active contact between the pair of gate electrodes, and outer spacers on side surfaces of the pair of gate electrodes. A distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern in the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned.