3D MOSFET Gate Structure With Dual Work Functions
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Solution Overview
Problem
The scaling down of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices leads to deteriorated operating characteristics, necessitating improved methods for fabricating semiconductor devices with enhanced reliability and electrical performance.
Innovation Solution
A semiconductor device design featuring stacked semiconductor patterns with alternating inner and outer gate electrodes, differing work functions, and a gate dielectric layer, along with a method of fabrication involving sacrificial pattern removal and metal layer etching to form a three-dimensional field effect transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFET sizes are scaled down to increase integration density, then device miniaturization is achieved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple semiconductor patterns are stacked vertically to form channel regions, enabling increased integration density without sacrificing device performance. The gate electrode wraps around these vertical stacks, providing control in multiple spatial dimensions and maintaining effective channel control despite miniaturization.
Solution Approach 2:
The channel region is divided into multiple discrete semiconductor patterns stacked vertically, with gate electrodes positioned between them. This segmentation allows each stacked channel to function as an independent conduction path while sharing common source and drain regions, thereby increasing effective channel area and improving operating characteristics within a reduced footprint.
2Reliability
If multiple gate electrodes are stacked to improve channel control, then device performance increases, but manufacturing complexity increases
Solution Approach 1:
The gate electrode structure serves multiple functions simultaneously: it provides electrical control over the channel, acts as a spacer defining channel width, and forms part of the fin structure. The gate dielectric layer similarly serves as both insulation and structural definition. This multi-functionality reduces the need for additional separate components, simplifying manufacturing despite the three-dimensional architecture.
Solution Approach 2:
Sacrificial patterns are formed in advance during manufacturing to define the precise positions and dimensions of the gate electrodes and channels. These sacrificial structures guide subsequent etching and deposition steps, ensuring accurate formation of the complex stacked geometry without requiring direct manual positioning of each layer.
3Reliability
If inner gate electrodes are positioned between semiconductor patterns, then channel control is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Gate dielectric layers are introduced as intermediary materials between the gate electrodes and semiconductor channel patterns. These dielectric layers provide precise spacing and positioning, acting as buffers that define the exact location of gate electrodes relative to the channels. The sacrificial patterns similarly serve as intermediaries during fabrication, temporarily holding structures in place to ensure correct final positioning.
Solution Approach 2:
The sacrificial patterns are formed beforehand to pre-establish the precise spatial relationships between all components. By defining the geometry of gate electrodes, channels, and spacers in advance through sacrificial structures, the actual fabrication steps can proceed with standard precision requirements, as the sacrificial masks guide material deposition and removal to the correct locations.
Data Source
AI summary
Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.