3D MOSFET Structure with Asymmetric Inner Gate Spacers
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved methods to enhance electrical performance and reliability.
Innovation Solution
A semiconductor device design featuring varying thicknesses of inner gate spacers between source/drain patterns, with a first inner gate spacer having a greater thickness than a second, along with a three-dimensional field effect transistor structure, to optimize spacing and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration density, then device integration is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns, enabling multiple channels to occupy the same footprint area. This dimensional change allows higher integration density while maintaining adequate channel dimensions for acceptable operating characteristics.
Solution Approach 2:
The channel pattern is divided into multiple vertically stacked segments (first channel pattern and second channel pattern), each with its own source/drain regions and gate electrodes. This segmentation enables independent optimization of each channel while achieving high overall integration.
2Manufacturing precision
If inner gate spacer thickness is increased to improve spacing control, then manufacturing precision is improved, but device area increases
Solution Approach 1:
Different inner gate spacer thicknesses are applied to different channel patterns based on their specific requirements. The first inner gate spacer has a first thickness while the second inner gate spacer has a second thickness, allowing localized optimization of spacing control without uniformly increasing device area.
Solution Approach 2:
The patent employs asymmetric inner gate spacer thicknesses where the first inner gate spacer thickness differs from the second inner gate spacer thickness. This asymmetry enables tailored spacing control for different channel patterns, improving manufacturing precision while minimizing overall device area increase.
Data Source
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AI summary
Disclosed is a semiconductor device comprising a substrate including first and second active patterns, first and second channel patterns on the first and second active patterns and each including first and second semiconductor patterns, first source/drain patterns connected to the first channel pattern, second source/drain patterns connected to the second channel pattern, a first inner gate electrode between neighboring first semiconductor patterns, a second inner gate electrode between neighboring second semiconductor patterns, a first inner gate spacer between the first inner gate electrode and the first source/drain pattern, and a second inner gate spacer between the second inner gate electrode and the second source/drain pattern. The first inner gate spacer has a first thickness. The second inner gate spacer has a second thickness. The first thickness is greater than the second thickness.