3D Gate-All-Around MOSFET Layout for Voltage Stability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties.
Innovation Solution
A semiconductor device design featuring a three-dimensional field effect transistor with a gate electrode that three-dimensionally surrounds the channel pattern, incorporating a high-k dielectric layer and a dielectric layer between the gate contact and electrode to manage voltage and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction to increase effective channel width and device density without increasing the lateral footprint, thereby maintaining small pattern size while improving operational properties through enhanced current drive capability
Solution Approach 2:
The gate electrode is designed to surround and wrap around the vertically stacked channel patterns in a three-dimensional configuration. This nested structure allows the gate to control multiple channels simultaneously, improving device performance and reliability while maintaining compact dimensions
2Reliability
If gate contact width is increased to reduce contact resistance, then electrical conductivity is improved, but voltage fluctuations increase
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the gate contact and the gate electrode. This dielectric layer acts as an insulating barrier that prevents direct electrical contact, thereby reducing contact resistance and improving electrical conductivity while stabilizing voltage by preventing unwanted charge injection or leakage from the wide gate contact to the gate electrode
Solution Approach 2:
The dielectric layer is selectively positioned only in the region where the gate contact overlaps with the gate electrode, providing localized insulation precisely where needed. This allows the gate contact to maintain its wider dimensions for low resistance while the dielectric layer prevents voltage fluctuations only at the critical interface region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves electrical and reliability characteristics of semiconductor devices by reducing voltage fluctuations and preventing reliability issues in high-power transistors.
Implementation Method 1
a gate insulating layer interposed between the first gate electrode and the first channel pattern
Implementation Method 2
a first dielectric layer interposed between the first gate contact and the first gate electrode
Data Source
AI summary
A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.