3D MRAM Cell Architecture Using Thin-Film Transistors
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Solution Overview
Problem
The use of MOS transistors as selection elements in magnetic random access memory (MRAM) and similar nonvolatile memories limits the arrangement into high-density three-dimensional designs due to long interconnects and high costs associated with three-dimensional MOS technology.
Innovation Solution
The implementation of thin-film transistors with a semiconductor layer and resistive memory elements, where the gate width is substantially larger than the element width, allowing for independent electrical coupling of conductive lines to resistive memory elements, enabling a more efficient and cost-effective three-dimensional memory cell architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOS transistors are used as selection elements in MRAM, then the memory can be manufactured with conventional processes, but the interconnect length increases and three-dimensional high-density arrangement becomes limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. Multiple memory layers are stacked vertically with shared bit lines, allowing memory elements to be arranged in the vertical dimension rather than only in the plane. This reduces interconnect length by placing memory elements closer together in 3D space while maintaining manufacturability through adapted fabrication processes.
Solution Approach 2:
The patent merges multiple memory layers vertically, sharing common bit lines and control structures. Adjacent memory layers share bit lines, reducing the total number of interconnects needed. This consolidation approach maintains ease of manufacture while significantly reducing interconnect length and enabling higher density through vertical integration.
2Quantity of substance
If three-dimensional MOS technology is used to achieve high-density memory arrangement, then memory density increases, but manufacturing cost increases
Solution Approach 1:
The patent achieves high memory density by stacking multiple memory layers vertically in the third dimension. This 3D arrangement increases the quantity of memory elements per chip area without requiring expensive three-dimensional MOS transistor technology. The vertical stacking uses adapted planar processes, avoiding the high costs associated with true 3D MOS fabrication while still achieving high density.
Solution Approach 2:
The patent implements shared bit lines that serve multiple adjacent memory layers simultaneously. This multi-functional approach allows a single bit line to be used by several layers, reducing the total number of interconnects required and lowering manufacturing complexity and cost while maintaining high memory density through vertical stacking.
3Reliability
If conventional MTJ with pinned and free ferromagnetic layers is used, then magnetic tunnel junction functionality is achieved, but the device area and complexity increase
Solution Approach 1:
The patent changes the magnetization orientation parameter from in-plane to perpendicular magnetization in the free ferromagnetic layer. This parameter change enables more stable magnetic states and allows for smaller device dimensions. The perpendicular magnetization configuration reduces the critical dimensions needed while maintaining reliable magnetic tunnel junction functionality, thereby reducing device area and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the density and reduces the cost of three-dimensional memory designs by allowing for independent selection and increased density of magnetic tunnel junctions, improving switching efficiency and reducing the required technology node.
Implementation Method 1
Magnetic random access memory (MRAM) using magnetic tunnel junctions (MTJs) is a strong candidate for providing a dense and fast non-volatile storage solution
Implementation Method 2
The free layer has a reversible magnetization direction that can have two stable directions which are parallel or anti-parallel to a fixed magnetization direction of the pinned layer. Resistance of the MTJ depends on the mutual orientation of the magnetization directions in the free and pinned layers and can be effectively controlled by an external magnetic field, a spin-polarized current or their combination.
Data Source
AI summary
A memory cell with a substrate; a first transistor comprising a first gate width and a terminal; resistive memory elements above the transistor, each element comprising an element width, a first and second end; parallel conductive lines above the first memory elements and coupled to the first elements at their first ends; a second plurality of resistive memory elements disposed above the conductive lines, each element comprising the width, the first end, and the second end and coupled to the conductive lines at their first ends; a second transistor disposed above the second plurality of resistive memory elements and comprising a gate width and a terminal, the first memory elements is jointly coupled to the terminal of the first transistor at their second ends; the second memory elements is jointly coupled to the terminal of the second transistor at their second ends; and the gate width is larger than the element width.