3D MRAM Integration via Wafer Cleaving and Vertical Stacking
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Solution Overview
Problem
Current 2D MRAM integration faces challenges in scaling below 20 nm due to complex integration of elements and limitations in bit density, with silicon channels struggling to handle high current loads during write operations, necessitating advanced memory technologies like spin torque MRAM and 3D integration for improved density.
Innovation Solution
The method involves forming a cleavable donor substrate with ion implantation and annealing to create blisters for wafer cutting, enabling 3D MRAM cell integration by stacking multiple layers vertically, using epitaxial Si layers for CMOS logic and pMTJs, and bonding techniques to overcome thermal and material limitations, allowing for higher density and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D MRAM integration is used, then manufacturing process is simpler, but bit density is limited and scaling below 20 nm is difficult
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by forming multiple layers of MRAM cells stacked in the vertical direction. This is achieved through sequential deposition of magnetic tunnel junction (MTJ) layers, spacer layers, and conductive layers, creating a three-dimensional structure that dramatically increases bit density while maintaining manufacturability through established semiconductor fabrication processes.
2Power
If silicon channels are used, then compatibility with CMOS logic is good, but high current loads during write operations cannot be handled
Solution Approach 1:
The patent applies different material properties to different regions of the device. Specifically, it uses cobalt-based ferromagnetic layers with perpendicular magnetic anisotropy in the MTJ structure to enable high current handling capability for write operations, while maintaining compatibility with standard CMOS fabrication processes. The local use of CoFeB and CoFe layers provides the necessary current handling capability without requiring complete replacement of the CMOS infrastructure.
3Quantity of substance
If multiple layers of MRAM stacks are stacked vertically, then density is improved, but thermal stress and strain on magnetic components increase
Solution Approach 1:
The patent segments the MRAM structure into multiple discrete layers separated by spacer layers and dielectric materials. Each MRAM cell layer is independently formed with its own set of MTJ layers, spacers, and conductive layers. This segmentation allows thermal stress to be managed at each interface rather than accumulating across the entire stack, enabling vertical stacking of multiple layers while controlling thermal stress on magnetic components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher density and capacity MRAM integration, potentially surpassing traditional 2D schemes by allowing multiple layers of MRAM stacks with reduced thermal stress and strain on magnetic components, while maintaining compatibility with CMOS logic and thermal budgets.
Implementation Method 1
implanting ions into a donor substrate to a peak implant position located below an upper surface of the donor substrate in a film thickness direction
Implementation Method 2
annealing the donor substrate and dielectric layer in an inert environment to form blisters at the peak implant position
Data Source
AI summary
In accordance with one embodiment, a method includes forming a cleavable donor substrate, the substrate including monocrystalline Si, forming a dielectric layer above the substrate in a film thickness direction, and cleaving the substrate into an upper portion having the dielectric layer and a lower portion. In one embodiment, the cleavable substrate is formed using a sacrificial buffer layer above the substrate in the film thickness direction, and forming a strained Si layer above the sacrificial buffer layer in the film thickness direction, followed by etching away the sacrificial buffer layer to cleave the substrate. In another embodiment, the cleavable substrate is formed by implanting ions into the substrate to a peak implant position located below an upper surface of the substrate, annealing the substrate and dielectric layer in an inert environment to form blisters at the peak implant position, and cleaving the substrate using the blisters.