3D Multi-Layered Logic Architecture for Data Reuse
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Solution Overview
Problem
Conventional CNN-based systems face inefficiencies due to high communication costs in large circuit designs, limiting the use of live data, particularly in processing large amounts of data, which necessitates improved data reuse techniques.
Innovation Solution
The implementation of a 3D multi-layered architecture with integrated circuit components arranged vertically, utilizing a memory array and inter-layer data bus to enhance data reuse, reducing SRAM reads and energy usage, and incorporating systolic arrays and processors for efficient data movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CNN-based systems use large circuit designs to process large amounts of data, then processing capability is improved, but communication cost increases excessively
Solution Approach 1:
The patent transitions from a conventional two-dimensional circuit layout to a three-dimensional stacked architecture. Multiple logic layers are vertically stacked above the memory array, with inter-layer data buses providing direct vertical data paths. This dimensional change enables simultaneous data access from multiple logic layers to the same memory array, dramatically increasing data reuse and reducing communication overhead between memory and processing units.
2Productivity
If conventional systems increase live data usage for better processing, then processing quality is improved, but communication overhead increases
Solution Approach 1:
The patent merges memory and logic functions into a tightly integrated 3D structure where the memory array and multiple logic layers form a unified processing system. The inter-layer data buses directly connect memory to multiple logic layers without requiring separate communication interfaces, reducing communication overhead while enabling efficient live data processing across multiple processing stages.
3Productivity
If conventional designs use more data paths for large data manipulation, then data throughput is improved, but wire length and physical cost increase
Solution Approach 1:
The patent utilizes the vertical dimension to create short data paths between memory and multiple logic layers. Instead of routing data through long horizontal wires across a large 2D chip, the 3D stacked architecture provides direct vertical connections via inter-layer data buses, dramatically reducing wire length while maintaining high data throughput capability.
Data Source
AI summary
Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.