3D Multichip Package Structure for Compact Chip Stacking
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Solution Overview
Problem
Current semiconductor IC technologies face challenges in scaling and innovating for expanded applications and business demands, requiring new approaches to integrate advanced semiconductor technology effectively.
Innovation Solution
The development of a three-dimensional multichip package formed by encapsulating or sealing separated chips using insulating materials like silicon dioxide, silicon oxynitride, and polymer materials, with various substrate options, and categorized into bonding structures and interposer configurations to enhance integration and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated using traditional planar packaging, then application volume is limited, but the need for expanded applications and business demands requires scaling
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional (3D) packaging by stacking multiple chips vertically. This dimensional change enables expanded application volume and business scalability without proportionally increasing packaging structure complexity, as the z-axis stacking provides efficient space utilization.
Solution Approach 2:
The patent implements nested packaging structures where chips are stacked within a package substrate, with upper chips positioned over lower chips. This nesting approach allows multiple functional layers to be integrated in a compact volume, enabling application expansion while maintaining manageable structural complexity through hierarchical organization.
2Productivity
If chips are separated and individually packaged, then manufacturing is simple, but integration efficiency and compactness are reduced
Solution Approach 1:
The patent merges multiple separately packaged chips into a single integrated 3D package structure. By combining multiple chips and their individual packaging into one unified package substrate assembly, integration efficiency is dramatically improved while the total package volume is reduced compared to separate packaging of each chip.
Solution Approach 2:
The patent utilizes vertical stacking in the z-axis dimension to achieve high integration efficiency. By arranging chips in three dimensions rather than spreading them out in two dimensions, the package volume is minimized while maintaining high productivity through efficient space utilization and reduced interconnect lengths.
3Reliability
If advanced semiconductor technologies are implemented, then performance is improved, but scaling to meet expanded business demands becomes challenging
Solution Approach 1:
The patent segments advanced semiconductor functionality into multiple discrete chips that can be independently fabricated using advanced processes, then integrated through 3D packaging. This segmentation allows each chip to be optimized for specific functions while the overall system scales to meet expanded business demands by adding or reconfiguring chip layers.
Solution Approach 2:
The patent creates a universal 3D packaging platform that can accommodate various chip types and configurations to meet different business demands. The modular package substrate and interconnection structures provide multi-functionality, enabling the same packaging technology to support diverse advanced semiconductor applications and scale flexibly.
Data Source
AI summary
A multi-chip package includes a first IC chip; a first sealing layer at a same first horizontal level as the first IC chip; a first silicon-oxide-containing layer over the first IC chip and first sealing layer and across an edge of the first IC chip; a first bonding pad in a first opening in the first silicon-oxide-containing layer, wherein the first bonding pad has a copper layer in the first opening; a second IC chip over the first IC chip; a second sealing layer at a same second horizontal level as the second IC chip; a second silicon-oxide-containing layer under the second IC chip and having a bottom surface bonded to and in contact with a top surface of the first silicon-oxide-containing layer; a second bonding pad under the second IC chip, in a second opening in the second silicon-oxide-containing layer and coupling to the second IC chip, wherein the second bonding pad has a copper layer in the second opening and having a bottom surface bonded to and in contact with a top surface of the copper layer of the first bonding pad; an interconnection scheme under the first IC chip and first sealing layer and across an edge of the first IC chip; and a metal bump under and in contact with the interconnection scheme, wherein the metal bump comprises tin.