3D Multi-Chip Module With Expanded Terminals For High Density Integration
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Solution Overview
Problem
Conventional silicon process technologies face challenges in achieving high-density integration and miniaturization due to limitations in packaging and mounting technologies, leading to increased costs and reduced integration density, particularly with ultrathin chips, and difficulties in testing and reliability of bare chips.
Innovation Solution
A multi-chip module structure with expanded terminal units and protective layers made of insulating materials, allowing for realigned terminals and extended wiring units that connect and align integrated circuit chips in three dimensions, enabling high-density integration and reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging and mounting technologies are used for high-density integration, then integration density can be improved, but manufacturing costs increase and miniaturization is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple chip layers are stacked vertically with through-silicon vias (TSVs) enabling inter-layer connections, achieving high-density integration in the vertical dimension while using standard silicon CMOS processes, thereby avoiding the need for expensive specialized packaging equipment and processes
Solution Approach 2:
The patent divides the integrated circuit into multiple separate chip layers that can be independently fabricated using standard silicon processes, then stacked and interconnected. This segmentation allows each layer to be optimized independently and enables high-density integration through vertical stacking without requiring expensive monolithic three-dimensional silicon process modifications
2Length of moving object
If ultrathin chips are used to reduce size, then miniaturization is improved, but mechanical strength and reliability deteriorate
Solution Approach 1:
The patent employs a composite structure where ultrathin active chip layers are combined with thicker structural support layers and encapsulation materials. The ultrathin chips (e.g., 50-200 micrometers) provide miniaturization while the composite construction with support substrates and protective encapsulation restores mechanical strength and reliability, enabling both size reduction and structural integrity
3Device complexity
If bare chips are used without packaging to reduce complexity, then device complexity is reduced, but testing and reliability verification become difficult
Solution Approach 1:
The patent performs wafer-level testing and verification before the chips are stacked and packaged. Electrical tests, functional verification, and reliability checks are conducted on the bare chips while they are still in wafer form or as individual unpackaged chips, allowing early detection of defects. This preliminary action ensures reliability is verified before final assembly, eliminating the need for complex post-packaging testing structures
Data Source
AI summary
A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.