3D Multichip Package Perimeter Vertical Interconnects
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Solution Overview
Problem
Three-dimensional multichip packages face challenges in achieving high connection speed and bandwidth due to limitations in through-dielectric via connections, and manufacturing yield is lower than individual components, with defective components rendering the entire package non-functional.
Innovation Solution
A multichip package design featuring an array of chip stacks separated by insulators with vertical connections through perimeter regions and a controller chip for dynamic control, allowing for higher interconnection speed and redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-dielectric vias are used to connect stacked chips, then connection density increases compared to wire bonding, but connection speed and bandwidth are limited by chip sizes
Solution Approach 1:
The patent moves vertical connections from the chip surface plane to the perimeter region outside the chip projection, effectively utilizing the third dimension (vertical space around the chip) to achieve shorter connection paths while maintaining high connection density through the dielectric layer
2Speed
If through-silicon vias are used for vertical connections, then connection speed and bandwidth improve, but manufacturing complexity and alignment challenges increase
Solution Approach 1:
The patent extracts the vertical connection function from the chip interior (through-silicon vias) and relocates it to the perimeter region through the dielectric layer, eliminating the need for complex through-silicon via fabrication while maintaining short connection paths
Solution Approach 2:
The dielectric layer serves as an intermediary medium that enables vertical connections between stacked chips in the perimeter region, simplifying the connection structure compared to through-silicon vias while maintaining electrical connectivity
3Volume of moving object
If multiple chips are stacked vertically to increase storage capacity, then form factor is reduced, but manufacturing yield decreases and defective components render the entire package non-functional
Solution Approach 1:
The patent segments the monolithic chip structure into multiple smaller chips stacked vertically, each with its own perimeter region for connections. This segmentation allows independent testing and replacement of individual chips, improving manufacturing yield and reliability while maintaining compact form factor
Data Source
AI summary
A structure of a multichip package and a method for fabricating the multichip package are described. The multichip package includes multiple chip stacks including chips in multiple chip layers. Each of the chip stacks includes two or more chips, each chip being inside vertical projection of at least another chip in the chip stack and disposed in a respective chip layer. Each of the chip stacks also includes horizontal conductive lines extending to perimeter regions around the chip stacks, the chips in a particular chip layer being electrically connected to horizontal conductive lines disposed in the particular chip layer. Each of the chip stacks also includes vertical conductive lines in the perimeter regions electrically connected to one or more of the horizontal conductive lines in at least two chip layers. The multichip package also includes a controller chip electrically connected to at least one chip in the chip stacks.