3D Multilayer Circuit Density via Vertical Crossbar Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the size of electronic elements in integrated circuits, limiting performance and density improvements, as traditional methods approach physical barriers, necessitating the development of three-dimensional circuits with multiple layers of interconnected circuitry.
Innovation Solution
A three-dimensional multilayer circuit is created by stacking crossbar arrays vertically above a CMOS layer, using vias to connect them, with programmable crosspoint devices at intersections, allowing unique addressing and enhanced density through area-distributed CMOS circuitry and memristive or memcapacitive technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar scaling is continued to increase circuit density, then manufacturing difficulty increases due to physical barriers, but three-dimensional stacking adds structural complexity
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical stacking by introducing multiple layers of crossbar arrays stacked above a CMOS layer. This dimensional change allows continued density improvement without further planar scaling, as circuits are arranged in the vertical dimension rather than continuing to shrink lateral features.
Solution Approach 2:
The patent implements nested structures where crossbar arrays are stacked vertically with each layer containing nanowire bundles that are themselves composed of multiple nanowires. The CMOS layer is nested at the bottom, with vias penetrating through intermediate insulating layers to connect successive crossbar layers, creating a compact nested architecture.
2Adaptability or versatility
If more vias and CMOS cells are added for unique addressing in 3D circuits, then addressing capability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent makes vias multi-functional by having them serve dual purposes: electrical connection between layers and unique addressing identifiers. Each via's spatial position encodes addressing information, allowing the same via structure to perform both connectivity and addressing functions without requiring separate addressing circuitry.
Solution Approach 2:
The patent changes the addressing parameter from electrical signals requiring additional CMOS cells to spatial position information encoded by via locations. This parameter change from functional circuitry to geometric encoding simplifies manufacturing by eliminating the need for additional addressing transistors and logic cells.
3Use of energy by moving object
If line length is reduced to minimize capacitance and resistance, then energy consumption decreases, but interconnect complexity in 3D stacking increases
Solution Approach 1:
The patent segments interconnect paths into short vertical via connections and horizontal nanowire segments within layers. By dividing the interconnect into these short segments rather than using long continuous traces, the total line length is minimized, reducing capacitance and resistance while maintaining connectivity across multiple layers.
Solution Approach 2:
The patent introduces insulating layers with embedded vias as intermediaries between crossbar layers. These intermediary structures provide localized vertical connections without requiring long interconnect paths, allowing signals to hop between layers through short via segments rather than traveling through complex long-distance interconnects.
Data Source
AI summary
A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template is then aligned with the first set of vias and lower crossbar segments are created using the template. The template is then removed, rotated, and aligned with the set of second vias. Upper crossbar segments which attach to the second set of vias are then created.