3D NAND Memory Stack with Air Cavities to Reduce Parasitic Capacitance
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Solution Overview
Problem
In three-dimensional semiconductor devices, such as vertical NAND strings, parasitic capacitance between bit lines and contact via structures contributes to increased RC delay, which affects device performance. This capacitance is exacerbated by capacitive coupling and requires reduction to enhance operational speed.
Innovation Solution
The implementation of low dielectric constant dielectric materials, vacuum cavities, or air cavities over contact via structures to minimize parasitic capacitance, along with specific arrangements of memory stack structures and bit lines, such as a five-folded memory stack configuration, to reduce electrical shorts and increase lithography margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional stacked memory structure is used, then device density is achieved, but parasitic capacitance between bit lines and contact via structures increases causing increased RC delay
Solution Approach 1:
The patent extracts and removes the harmful dielectric material surrounding the contact via structures, replacing it with vacuum or air cavities. This extraction eliminates the parasitic capacitance source while preserving the underlying memory structure and contact functionality.
Solution Approach 2:
The patent introduces porous vacuum or air cavity structures around the contact via structures. These porous regions provide electrical isolation and reduce parasitic capacitance while maintaining structural integrity and enabling continued scaling of the memory device.
2Quantity of substance
If more memory stack structures are arranged in rows, then device capacity increases, but lithography precision requirements increase due to reduced spacing
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional configuration where memory stack structures are arranged in multiple rows with lateral offsets. This dimensional change allows increased device capacity without proportionally reducing the lithography pitch, as the offset arrangement provides additional spatial separation.
Solution Approach 2:
The patent employs asymmetric positioning of contact via structures relative to the memory stack structures, with lateral offsets between adjacent rows. This asymmetric arrangement optimizes the spacing and alignment requirements, reducing the stringency of lithography precision needed for manufacturing.
3Reliability
If contact via structures are positioned directly over memory stack structures, then electrical connection is optimized, but electrical shorts may occur between adjacent structures
Solution Approach 1:
The patent introduces vacuum or air cavity regions as intermediary spaces between adjacent contact via structures and memory stack structures. These intermediary regions provide electrical isolation, preventing shorts while allowing the contact via structures to maintain their electrical connection to the underlying memory stack structures through the centered positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduction in parasitic capacitance leads to decreased RC delay, improved operational speed, and increased performance of three-dimensional semiconductor devices by minimizing electrical shorts and enhancing lithography margins, thereby optimizing device configuration and functionality.
Implementation Method 1
parasitic capacitance between bit lines and contact via structures contributes to increased RC delay
Implementation Method 2
implementation of low dielectric constant dielectric materials, vacuum cavities, or air cavities over contact via structures to minimize parasitic capacitance
Data Source
AI summary
A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.