3D NAND Memory Stack Air Gap Fabrication
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Solution Overview
Problem
As 3D NAND devices scale, the increasing aspect ratio of memory cell strings leads to challenges in etching and stress control, making downstream processes more difficult, particularly in maintaining manageable limits and achieving efficient word-line isolation.
Innovation Solution
A method and apparatus for forming nonvolatile memory cells in 3D NAND structures by creating a stack of alternating layers, forming memory holes, depositing blocking oxide and silicon, filling with core oxide, and removing one layer to create spaces that are either partially filled with a third material to leave air gaps or fully filled with a low k oxide, using materials like carbon, ruthenium, and low k oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked memory cells increases to achieve higher densities, then storage capacity improves, but the aspect ratio of memory cell strings increases making etching and stress control more difficult
Solution Approach 1:
The patent segments the memory cell string structure by introducing alternating conductor and insulator layers, creating a modular stacked architecture. This segmentation allows the high-density storage to be achieved through multiple discrete layers rather than a single continuous structure, making the manufacturing process more manageable despite the increased aspect ratio
Solution Approach 2:
The patent applies local quality by using different materials with specific properties at different locations within the stack. Conductive layers are placed where electrical connectivity is needed, while insulator layers are positioned for isolation and stress management. This localized material assignment optimizes both storage capacity and manufacturability at different heights of the cell string
2Length of stationary object
If layer thickness is reduced to maintain manageable aspect ratio, then etching difficulty decreases, but downstream etch processes become more challenging
Solution Approach 1:
The patent changes the physical and chemical parameters of the layers, specifically using alternating conductor and insulator materials with different etch selectivities. This parameter change allows downstream etch processes to differentiate between layer types, maintaining manufacturing precision even as layer thickness is reduced to control aspect ratio
3Ease of manufacture
If conventional replacement metal gate processes are used, then manufacturing is simplified, but word-line isolation and cross-talk reduction are insufficient
Solution Approach 1:
The patent extracts the word-line isolation function from the conventional metal gate process by introducing a dedicated insulator layer between conductor layers. This extracted isolation layer specifically addresses cross-talk reduction between adjacent word lines, improving reliability without complicating the overall manufacturing process
Solution Approach 2:
The insulator layers serve as intermediary elements between the conductive word-line layers. These intermediary insulator layers physically separate and electrically isolate adjacent conductors, preventing cross-talk while maintaining the simplicity of the deposition-based manufacturing approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves word-line isolation, reduces cross-talk between memory cells, and simplifies high aspect ratio etch and gap fill processes, allowing for a thinner stack height and eliminating the need for conventional replacement metal gate processes, thereby addressing manufacturing issues and enhancing electrical performance.
Implementation Method 1
depositing a layer of blocking oxide on sides defining the memory hole
Implementation Method 2
depositing core oxide to fill the silicon channel
Implementation Method 3
forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material
Data Source
AI summary
Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.