3D NAND Memory Hole Structure With Air Gaps for Lower Cell Interference
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Solution Overview
Problem
The challenge in 3D NAND flash memory is to control cell-to-cell interference effectively as z-pitch scaling reduces inter-cell separation, leading to increased parasitic capacitance and performance degradation.
Innovation Solution
The method involves forming air gap structures between the gate/word line layers by creating recessed areas, depositing blocking oxide and charge trap material, and converting dummy layers into air gaps through a thermal treatment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If z-pitch scaling is performed to increase bit density, then the number of stacked memory cells increases, but inter-cell separation is reduced leading to increased parasitic capacitance
Solution Approach 1:
The patent extracts the harmful dielectric material from between the memory stacks and replaces it with air gaps. By removing the solid inter-gate spacer material in the regions between stacks, the parasitic capacitance is reduced while maintaining the vertical stacking density for high bit density.
Solution Approach 2:
The patent applies different structures to different regions: air gaps are formed between memory stacks where parasitic capacitance reduction is needed, while the inter-gate spacer material is retained within each stack where structural support and electrical isolation are required. This local differentiation resolves the contradiction between density and capacitance.
2Length of stationary object
If inter-gate spacer layers are reduced in thickness for z-scaling, then vertical scaling is achieved, but cell-to-cell interference increases
Solution Approach 1:
The patent removes the inter-gate spacer material from the regions between memory stacks by forming recesses and filling them with air gaps. This extraction eliminates the source of parasitic capacitance and cell-to-cell interference while preserving the reduced spacer thickness needed for vertical scaling.
Solution Approach 2:
The patent introduces air gaps (inert atmosphere) between the memory stacks to provide electrical isolation. The air environment has very low dielectric constant, which minimizes parasitic capacitance and cell-to-cell interference, allowing thin inter-gate spacers to be used without compromising isolation.
3Ease of manufacture
If continuous charge trap layer is used, then manufacturing is simpler, but retention performance degrades due to increased inter-cell interference
Solution Approach 1:
The patent segments the charge trap layer into discrete portions, each associated with a specific memory stack. The charge trap material is deposited conformally and then selectively removed from regions between stacks, creating isolated charge trap segments that prevent interference between cells while maintaining manufacturing feasibility through standard deposition and etch processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces inter-cell interference by utilizing the low dielectric constant of air gaps, improving retention performance of each cell, and minimizing the risk of structural defects in the layer stack.
Implementation Method 1
subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure
Data Source
Figure 1a~1b
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AI summary
According to an aspect, there is provided a method for forming a memory structure for a 3D NAND flash memory, the method comprising: forming a layer stack over a substrate; forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back gate layers of the layer stack from the memory hole; forming a lateral memory stack in each first recessed areas, by depositing a blocking oxide and, subsequently, a charge trap material; forming second recessed areas in the sidewall by laterally etching back the inter-gate spacer layers from the memory hole; forming dummy layers in the second recessed areas; lining the sidewall of the memory hole with a liner layer; subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure; forming a tunneling oxide layer in the memory hole, along the liner layer, and a channel layer along the tunneling oxide layer.