3D NAND Memory Structure With Air Gaps for Inter-Cell Isolation
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Solution Overview
Problem
The challenge in 3D NAND flash memory is to control cell-to-cell interference effectively, especially as z-pitch scaling reduces inter-cell separation, leading to increased parasitic capacitance and performance degradation.
Innovation Solution
The introduction of air gap structures between the gate/word line layers helps to efficiently control cell-to-cell interference. This is achieved by forming a layer stack with alternating gate and inter-gate spacer layers, creating recessed areas, depositing blocking oxide and charge trap material, and converting dummy layers into air gap structures through thermal treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If z-pitch scaling is used to increase bit density, then the number of stacked memory cells increases, but inter-cell separation is reduced leading to increased parasitic capacitance and cell-to-cell interference
Solution Approach 1:
The patent divides the continuous inter-gate spacer structure into segmented regions by introducing air gap structures between adjacent gate layers. This segmentation isolates electric fields between memory cells, reducing parasitic capacitance and cell-to-cell interference while maintaining high vertical stacking density for increased bit density.
Solution Approach 2:
The patent introduces air gap structures as intermediary elements between adjacent gate layers and memory cells. These air gaps act as electrical isolators with low dielectric constant, mediating the electric field interactions and reducing parasitic capacitance between closely spaced cells in vertically stacked configurations.
2Length of moving object
If inter-gate spacer layers are made thinner to achieve z-scaling, then vertical scaling is achieved, but parasitic capacitance between word lines increases
Solution Approach 1:
The patent applies local quality modification by introducing air gap structures at specific locations between gate layers where parasitic capacitance is most problematic. The inter-gate spacer layers maintain thin thickness for scaling while air gaps are strategically placed in regions of high electric field concentration to locally reduce parasitic capacitance without compromising overall structural integrity.
Solution Approach 2:
The patent creates a composite structure combining thin inter-gate spacer layers with air gap regions. This composite approach allows the spacer layers to provide mechanical support and electrical isolation while air gaps contribute low dielectric constant properties, achieving both thin thickness for scaling and reduced parasitic capacitance through material composition optimization.
3Ease of manufacture
If continuous charge trap layer is used, then manufacturing is simpler, but retention performance degrades due to reduced inter-cell separation
Solution Approach 1:
The patent segments the continuous charge trap layer into discrete sections associated with individual memory cells by positioning air gap structures between them. This segmentation prevents charge leakage between adjacent cells caused by reduced inter-cell separation, improving retention performance while maintaining relatively simple manufacturing through conformal deposition processes that naturally form continuous layers which are then electrically isolated by air gaps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of memory structures with discrete lateral memory stacks separated by air gap structures, reducing inter-cell interference and improving retention performance by minimizing parasitic capacitance.
Implementation Method 1
subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure
Implementation Method 2
convert each dummy layer into an air gap structure
Data Source
AI summary
According to an aspect, a method of forming a memory structure for a 3D NAND flash memory includes forming a layer stack over a substrate, forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back gate layers of the layer stack from the memory hole, and forming a lateral memory stack in each first recessed areas, by depositing a blocking oxide and, subsequently, a charge trap material. The method also includes forming second recessed areas in the sidewall by laterally etching back the inter-gate spacer layers from the memory hole and forming dummy layers in the second recessed areas. The method also includes lining the sidewall of the memory hole with a liner layer, subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure, and forming a tunneling oxide layer in the memory hole, along the liner layer, and a channel layer along the tunneling oxide layer.