3D NAND Inter-Wordline Airgap Structure for Lower RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D NAND memory arrays face challenges in reducing RC delay and capacitance between wordlines, leading to degraded reliability and performance due to high dielectric constants and leakage/cross talk issues, which are not effectively addressed by existing technologies.
Innovation Solution
The introduction of inter-wordline airgaps with a dielectric constant of 1.0 between wordlines, formed by replacing sacrificial silicon oxide with voids, reduces capacitance by approximately a factor of 4, enhancing performance and scalability without compromising floating gate memory cell integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials with high dielectric constants are used between wordlines, then capacitance between wordlines increases, but RC delay increases and reliability degrades
Solution Approach 1:
The patent removes the conventional dielectric material (silicon oxide) between wordlines and replaces it with airgaps (voids). This extraction of the harmful dielectric material eliminates the source of high capacitance and leakage, directly reducing RC delay while improving reliability. The airgap formation process involves removing sacrificial silicon oxide layers and replacing them with void spaces between adjacent wordlines.
Solution Approach 2:
The patent fundamentally changes the dielectric constant parameter from approximately 3.9 (silicon oxide) to 1.0 (air/vacuum) by introducing airgaps between wordlines. This parameter change results in approximately a 4× reduction in capacitance between wordlines, directly addressing the RC delay issue while maintaining electrical isolation functionality.
2Reliability
If conventional dielectric materials are used between wordlines, then structural support is provided, but leakage and cross talk between wordlines occur
Solution Approach 1:
The patent converts the potential harm of complete dielectric removal (loss of structural support) into a benefit by using airgaps that provide both electrical isolation and mechanical support through the underlying substrate and surrounding structures. The airgaps eliminate leakage and cross-talk pathways while the rigid substrate and surrounding dielectric layers provide the necessary structural support, turning a potential weakness into a performance advantage.
Solution Approach 2:
The patent uses air (gas) as the dielectric medium between wordlines instead of solid dielectric materials. These airgaps act as pneumatic insulators that provide excellent electrical isolation properties, preventing leakage and cross-talk between adjacent wordlines while maintaining the necessary physical separation.
3Productivity
If more wordlines are stacked vertically to increase density, then memory capacity increases, but RC delay and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D stacking by introducing airgaps between vertically stacked wordlines. This dimensional change allows for higher memory density by utilizing the vertical dimension more effectively, accommodating more wordlines and memory cells per unit area while the airgap structure simplifies the manufacturing process by providing a clear separation between stacking layers.
Solution Approach 2:
The patent segments the continuous dielectric structure into discrete airgap regions between individual wordlines. This segmentation provides clear electrical isolation between each wordline layer, simplifying the manufacturing process by allowing independent formation and testing of each wordline stack, thereby reducing overall manufacturing complexity despite increased vertical density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a 4× reduction in RC delay, improves array performance, reduces cell-to-cell interference, and increases breakdown voltage, maintaining or improving cell capabilities while allowing for vertical scalability and reduced wafer warpage.
Implementation Method 1
The introduction of inter-wordline airgaps with a dielectric constant of 1.0 between wordlines, formed by replacing sacrificial silicon oxide with voids, reduces capacitance by approximately a factor of 4
Data Source
AI summary
An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.