3D NAND Stack and Mold Layout for Alignment Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions, featuring stack structures with gate electrodes and channel structures, along with mold structures containing sacrificial layers, where the number of lower horizontal sacrificial layers is less than the number of lower gate electrodes, optimizing the alignment and spacing to enhance reliability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of lower horizontal sacrificial layers is made equal to the number of lower gate electrodes to simplify manufacturing, then manufacturing precision deteriorates due to misalignment and defects in the third region
Solution Approach 1:
The substrate is divided into three distinct regions: a first region with stack structures, a second region with mold structures, and a third region with both stack and mold structures. This segmentation allows different manufacturing approaches in different regions, with the third region serving as a transition zone that ensures alignment precision while maintaining manufacturing simplicity in other areas.
Solution Approach 2:
Different regions of the substrate are assigned different numbers of sacrificial layers based on local requirements. The first and second regions have fewer sacrificial layers for simplicity, while the third region has an increased number of sacrificial layers matching the gate electrodes to ensure precise alignment in this critical transition zone.
2Quantity of substance
If three-dimensional memory cell arrangements are implemented to increase storage capacity, then device complexity increases making manufacturing and alignment more difficult
Solution Approach 1:
The patent transitions from traditional two-dimensional planar memory cell arrangements to three-dimensional vertically stacked memory cell structures. Multiple gate electrodes are stacked vertically above the substrate, with channel structures penetrating through these stacks, thereby increasing storage capacity by utilizing the vertical dimension while managing complexity through systematic regional division.
3Manufacturing precision
If alignment structures extend through all mold structures to ensure proper positioning, then device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
Alignment structures are selectively implemented only in the third region where both stack and mold structures coexist, rather than extending through all mold structures across the entire substrate. This localized approach ensures proper positioning in the critical transition zone while avoiding unnecessary complexity in regions where alignment structures are not needed.
Data Source
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AI summary
A semiconductor device (100) includes a substrate (101) having a first region (R1) and a second region (R2); a first stack structure (GS1) including lower gate electrodes (130) stacked in a first direction (Z) in the first region (R1); a first channel structure (CH1) penetrating through the first stack structure (GS1); a second stack structure (GS2) on the first stack structure (GS1) and the first channel structure (CH1) and including upper gate electrodes (130) stacked in the first direction (Z); a second channel structure (CH2) penetrating through the second stack structure (GS2); a first mold structure (KS1) including lower horizontal sacrificial layers (180) stacked in the first direction (Z) in the second region (R2); an alignment structure (KC) penetrating through the first mold structure (KS1); and a second mold structure (KS2) on the first mold structure (KS1) and the alignment structure (KC) and including upper horizontal sacrificial layers (180) stacked in the first direction (Z), wherein the number of the lower horizontal sacrificial layers (180) is less than the number of the lower gate electrodes (130).