3D NAND Channel Structure With Back Gate Segmentation
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Solution Overview
Problem
There is a need for semiconductor devices with increased data storage capacity, and existing two-dimensional memory cell arrangements are limited in this regard.
Innovation Solution
A semiconductor device is designed with a back gate structure that divides channel structures into multiple portions, utilizing a back gate electrode and back gate line regions to enhance data storage capacity by creating a three-dimensional arrangement of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed two-dimensionally, then device structure is simple and manufacturing is easier, but data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by introducing vertical channel holes penetrating through stacked gate electrodes and interlayer insulating layers. This dimensional change allows memory cells to be arranged in three dimensions, significantly increasing data storage capacity while managing structural complexity through systematic layering.
Solution Approach 2:
The patent divides the channel structure into multiple segments by introducing back gate structures that split each channel into first and second channel portions. This segmentation allows independent control of different channel regions, enabling enhanced storage capacity through multi-state memory cells while maintaining manufacturability through modular structure design.
2Quantity of substance
If back gate structure divides channel into multiple portions, then data storage capacity increases, but device structure becomes more complex
Solution Approach 1:
The back gate structure serves multiple functions: it divides the channel into multiple portions for increased storage capacity, provides independent control regions for multi-state memory operation, and maintains structural integrity through the integrated design of back gate electrode regions and back gate line regions. This multi-functionality justifies the increased structural complexity by delivering proportional performance benefits.
3Quantity of substance
If three-dimensional arrangement is implemented, then storage density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning actions where channel holes are formed first, followed by sequential deposition and patterning of gate electrodes and interlayer insulating layers. This step-by-step preliminary action approach allows precise alignment in three dimensions by establishing reference structures before adding subsequent layers, thereby achieving high storage density while managing manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes a source structure, a stack structure including interlayer insulating layers and gate electrodes stacked in a first direction perpendicular to an upper surface of the source structure, channel structures disposed in channel holes, penetrating the stack structure in the first direction, the channel structures including a gate dielectric structure and a channel layer, a back gate structure dividing each of the channel structures into a first channel portion and a second channel portion and extending in a second direction perpendicular to the first direction. The back gate structure includes back gate electrode regions disposed between the first channel portion and the second channel portion in each of the channel structures of each of the channel structures, and filling the channel hole, and back gate line regions penetrating the stack structure and connecting the back gate electrode regions to each other in the second direction.