3D NAND Flash Memory Background Reads for Floating Body Effect
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Solution Overview
Problem
3D NAND flash memory arrays experience a higher than normal number of bit errors during the first data read operation due to residual charge accumulation in the channel body, known as the 'floating body effect,' which interferes with the initial sensing of floating gate states and causes misreads in memory cells.
Innovation Solution
A program/read control circuit performs background reads on stacked memory cells to stabilize them, with a timer circuit ensuring these reads occur over selected time intervals, adapting to workload requirements and reducing the observed raw bit error rate (RBER) by refreshing each erasure block before a first normal read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If background reads are performed frequently to stabilize memory cells and reduce bit error rates, then reliability improves, but productivity deteriorates due to increased overhead processing time
Solution Approach 1:
The patent implements periodic background read operations at predetermined time intervals to stabilize memory cells. The controller performs these background reads on a recurring basis, selecting different erasure blocks at each interval, which systematically reduces bit error rates without requiring continuous operation that would overwhelm host I/O performance.
Solution Approach 2:
The background read operations are performed continuously in the background during normal device operation, rather than interrupting host I/O commands. This continuous stabilization process occurs concurrently with data transfer operations, maintaining reliability improvements while minimizing impact on productivity.
2Measurement precision
If background reads are performed on all erasure blocks systematically, then measurement precision improves by reducing floating body effect, but device complexity increases due to block tracking and scheduling requirements
Solution Approach 1:
The patent divides the memory array into multiple erasure blocks and systematically selects different blocks for background reads at each time interval. This segmentation approach ensures comprehensive coverage of all blocks over time, improving overall read accuracy through the floating body effect mitigation while distributing the control complexity across manageable block units.
Data Source
AI summary
Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.