3D NAND Backside Contact Pads for Low-Capacitance Stacked Arrays
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Solution Overview
Problem
The formation of contacts in 3D NAND memory devices can cause parasitic capacitance, affecting high-speed operation, and the polysilicon layer in the first array device may not receive sufficient hydrogen for defect repair, leading to incomplete crystallographic defect repair.
Innovation Solution
A fabrication method that includes forming channel holes and gate line slits in the 3D array device, followed by selective etching and deposition of semiconductor and conductive materials to create interconnects and contacts, ensuring adequate hydrogen access to the polysilicon layer and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are formed in the first and second array devices to connect contact pads to the peripheral device, then electrical connection is achieved, but parasitic capacitance increases affecting high-speed operation
Solution Approach 1:
The patent removes the contact structure from the first array device, keeping contacts only in the second array device. This extraction eliminates the parasitic capacitance source in the first array device while maintaining necessary electrical connections through the remaining contact structure in the second array device.
Solution Approach 2:
The patent introduces a conductive layer that extends from the contact pad through the first array device to the second array device, serving as an intermediary conductor. This allows electrical connection without requiring discrete contacts in the first array device, thereby reducing parasitic capacitance while maintaining connectivity.
2Quantity of substance
If the second array device is stacked above the first array device to increase density, then storage capacity increases, but the polysilicon layer in the first array device does not receive sufficient hydrogen for defect repair
Solution Approach 1:
The patent segments the hydrogen delivery path by creating a dedicated hydrogen access channel that bypasses the second array device. This segmentation allows hydrogen to reach the polysilicon layer in the first array device independently, ensuring defect repair capability is maintained despite the stacked configuration.
Solution Approach 2:
The patent introduces a horizontal hydrogen access path through the substrate, changing from a vertical delivery approach that would be blocked by the second array device. This dimensional change allows hydrogen to reach the first array device polysilicon layer from the side, bypassing the stacked structure obstruction.
Data Source
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AI summary
Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes preparing a stacked device having a first array device and a second array device, forming an opening on a back side of the second array device, and forming one or more contact pads in the opening. The first array device includes first front pads on a face side of the first array device and first back pads on a back side of the first array device. The second array device includes second front pads on a face side of the second array device and bonded with the first back pads. The one or more contact pads are disposed at a level proximate to the second front pads with respect to the first array device.