3D NAND Insulating Layer Collapse Prevention via Barrier Patterns
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in manufacturing due to the inclination or collapse of insulating layers during the replacement of sacrificial layers with conductive layers, leading to reduced yield and device characteristics.
Innovation Solution
A semiconductor device structure and manufacturing method involving alternately stacked sacrificial and insulating layers, with specific opening formations and layer deposition techniques to control the placement and growth of metal layers, using barrier and dielectric patterns to prevent unwanted deposition and growth, ensuring stable and high-yield production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sacrificial layers are replaced with conductive layers in three-dimensional nonvolatile memory devices, then the device achieves higher storage capacity through vertical stacking, but the insulating layers become inclined or collapsed during the replacement process, reducing yield and device characteristics
Solution Approach 1:
The patent applies preliminary action by forming support structures (such as mandrels or framework elements) within the insulating layers before the sacrificial layer replacement process. These pre-formed supports prevent the insulating layers from collapsing or becoming inclined during subsequent manufacturing steps, thereby maintaining structural integrity while enabling vertical stacking for increased storage capacity
Solution Approach 2:
The patent introduces intermediary support structures that act as mediators between the sacrificial layers and the final conductive layers. These intermediaries provide temporary mechanical support to the insulating layers during the replacement process, preventing deformation and collapse, and are subsequently removed or replaced to complete the device fabrication
2Productivity
If insulating layers are stacked to form three-dimensional structures, then vertical stacking enables higher integration, but the layers are prone to inclination and collapse during manufacturing processes
Solution Approach 1:
The patent segments the insulating layers into smaller, individually supported sections rather than continuous large-area layers. By dividing the structure into manageable segments with localized support elements, each segment can be independently stabilized during fabrication, preventing cumulative deformation and enhancing overall structural stability for high-density vertical stacking
Solution Approach 2:
The patent employs composite material structures combining insulating layers with embedded support materials that provide mechanical reinforcement. These composite structures integrate the electrical insulation properties with enhanced mechanical strength, enabling stable vertical stacking while maintaining the required electrical isolation between layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a stable structure and high production yield for three-dimensional semiconductor devices by controlling the placement of conductive layers and preventing unwanted deposition, resulting in improved device characteristics and integration.
Implementation Method 1
depositing metal layers on the barrier layers exposed by the deposition-preventing layers
Implementation Method 2
forming deposition-preventing layers on the barrier layers exposed through the first openings
Implementation Method 3
growing metal layers from the seed layers exposed by the growth-preventing layers
Data Source
AI summary
A semiconductor device may include semiconductor patterns. The semiconductor device may include insulating layers including first regions surrounding the semiconductor patterns and second regions isolated from each other by island-type first openings and connecting the first regions adjacent to each other. The semiconductor device may include metal layers interposed between the first regions of the stacked insulating layers surrounding the semiconductor patterns, and isolated from each other by line-type second openings overlapping the first openings and the second regions. The semiconductor device may include dielectric patterns partially interposed between the insulating layers and the metal layers and exposed through the second openings.