3D NAND Memory Bit Line Grouping for Selective Erase
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Solution Overview
Problem
As the number of memory cells in a memory array increases, the size of the memory block also increases, leading to inefficient erase operations where too many memory cells are erased at once, affecting the lifetime and electrical characteristics of semiconductor devices.
Innovation Solution
The semiconductor device classifies bit lines into groups and uses an operation circuit to apply specific voltages to selected groups for erase operations, allowing for more targeted and efficient erase operations on memory strings, rather than the traditional memory block basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in a memory array is increased, then the storage capacity is improved, but the size of the memory block increases leading to inefficient erase operations
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks, where each sub-block contains a portion of the memory cells connected to specific bit lines. The erase operation is then performed on selected sub-blocks rather than the entire memory block, allowing selective erasure of only the necessary memory cells while preserving others. This segmentation resolves the contradiction by enabling efficient erase operations even as the total number of memory cells increases.
2Ease of operation
If erase operation is performed on a memory block basis, then the operation is simple to control, but too many memory cells are erased affecting device lifetime
Solution Approach 1:
The memory block is segmented into sub-blocks that can be independently erased. The operation circuit is configured to receive erase commands for specific sub-blocks and apply erase voltages only to the bit lines associated with those sub-blocks. This maintains operational simplicity while improving reliability by minimizing the number of memory cells subjected to erase operations, thereby reducing erase disturbance and extending device lifetime.
Solution Approach 2:
Different regions (sub-blocks) of the memory block are treated differently during erase operations. Instead of uniformly erasing the entire memory block, the operation circuit applies erase voltages locally to only those sub-blocks that require erasure. This local approach reduces the overall impact on device lifetime while maintaining the ability to perform complete erasures when necessary.
3Reliability
If erase voltage is applied to all bit lines, then the erase operation is comprehensive, but the erase disturbance to non-selected memory cells increases
Solution Approach 1:
The bit lines are divided into multiple groups, with each group associated with specific sub-blocks of memory cells. During an erase operation, the operation circuit applies erase voltages only to the bit line groups corresponding to the selected sub-blocks. This segmentation ensures comprehensive erasure of the intended memory cells while preventing erase disturbance to memory cells in other sub-blocks, thus resolving the contradiction between erase completeness and minimizing harmful effects.
Data Source
AI summary
A semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation.