3D NAND Program Operations for Bit-Line Disturbance Control
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Solution Overview
Problem
The increased number of layers in 3D NAND flash memory leads to program disturbance in memory cells not selected for programming, narrowing their read windows and degrading memory performance.
Innovation Solution
By maintaining a constant programming voltage in the last few program loops and applying an inhibit voltage followed by discharge to unselected bit lines, the program disturbance is reduced while maintaining programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in 3D NAND flash memory is increased to achieve higher storage density, then storage capacity is improved, but program disturbance in non-selected memory cells increases and read windows narrow
Solution Approach 1:
The patent segments the bit line voltage control into different phases: during early program loops, inhibit voltage is applied to all unselected bit lines; during late program loops, only specific unselected bit lines receive inhibit voltage while others are discharged. This segmented approach allows selective suppression of program disturbance while maintaining programming efficiency, resolving the contradiction between high-density storage and read window preservation
Solution Approach 2:
The patent dynamically adjusts bit line voltage control strategies based on program loop progression. In early loops, comprehensive inhibit voltage application prevents program disturbance. In late loops, selective discharge of certain unselected bit lines optimizes the balance between preventing disturbance and maintaining programming speed, enabling the system to adapt to changing conditions during the program operation
2Reliability
If inhibit voltage is applied to unselected bit lines during program operations, then program disturbance is reduced, but programming efficiency decreases
Solution Approach 1:
The patent implements periodic action by applying inhibit voltage to unselected bit lines only during specific program loops (early and late stages) while discharging them during intermediate loops. This periodic application of inhibit voltage reduces program disturbance when most needed while minimizing the impact on programming efficiency during intermediate stages, thus resolving the contradiction between reliability and productivity
Solution Approach 2:
The patent changes the voltage parameter of unselected bit lines dynamically: applying inhibit voltage during early and late program loops to prevent program disturbance, and discharging during intermediate loops to maintain programming efficiency. This parameter change strategy allows the system to optimize both program disturbance reduction and programming efficiency at different stages of the program operation
Data Source
AI summary
Example memory devices, systems, and methods for reducing program disturbance in memory devices are disclosed. One example method includes during an n-th loop of a program operation performed on a first memory cell in a memory cell array, applying a first voltage to a first bit line coupled to a second memory cell in the memory cell array, where the first memory cell and the second memory cell are coupled to a first word line. The first bit line is discharged to decrease a voltage of the first bit line from the first voltage to a second voltage, where the second voltage is lower than the first voltage. After the first voltage is applied to the first bit line, a second bit line is set to floating, where the second bit line is coupled to the first memory cell.