3D NAND Bit-Line Switching Across Dual Multilayer Stacks

The device is divided into multiple stacked layers, each containing memory cells and associated bit lines. The bit lines are segmented into first bit lines in a lower layer and second bit lines in an upper layer, with each segment serving specific memory cells in its layer. This segmentation allows independent routing and connection of bit lines in each layer, reducing the overall integration complexity while maintaining high storage capacity through vertical stacking.

The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. Memory cells are arranged in multiple layers stacked in the vertical dimension, with bit lines extending through intermediate insulating layers to connect cells across layers. This dimensional change enables significantly increased storage capacity without proportionally increasing planar area or connection complexity.

Bit lines are segmented into separate first bit lines for lower layer memory cells and second bit lines for upper layer memory cells. This segmentation enables simultaneous or independent access to different layers through dedicated bit line paths, reducing access conflicts and improving overall data retrieval speed while maintaining high storage capacity through vertical stacking.

Intermediate insulating layers serve as mediators between lower and upper layer bit lines. These insulating layers contain openings that allow bit lines to extend vertically through the stack, providing direct electrical connection paths between control circuits and memory cells in different layers without requiring complex through-silicon vias or trenches, thereby improving access speed.