3D NAND In-Memory Search Using Bitwise Page Comparison
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Solution Overview
Problem
Conventional in-memory searching methods for three-dimensional NAND flash memory circuits require physical redesign of input/output interfaces and driving paths, limiting data width and hindering efficiency improvements.
Innovation Solution
A memory device and method that includes an address scanner, searching data transmitter, readout data sensor and comparator, error bit detector, and matching status processor to increase data width by bit-by-bit comparison of readout and search data within a memory page, using XOR and XNOR operations and wild card flags for ternary data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional in-memory searching methods are used for three-dimensional NAND flash memory circuits, then the input/output interface and driving path can be maintained, but the data width of search data is limited by the number of word lines and physical redesign is required
Solution Approach 1:
The patent segments the search data processing into multiple parallel comparison operations across different word lines. Instead of requiring physical redesign for increased data width, the system divides the search space into segments that can be processed simultaneously through multiple word lines, thereby increasing effective data width without changing the fundamental I/O interface structure.
Solution Approach 2:
The patent introduces a time dimension to the searching process by implementing sequential scanning across multiple word lines. This allows the system to achieve increased data width capability through temporal multiplexing rather than spatial expansion, maintaining the same physical I/O interface while effectively processing wider data through repeated operations.
2Productivity
If the data width of search data is limited by the number of word lines, then the conventional memory structure can be used, but the efficiency of searching operations cannot be improved
Solution Approach 1:
The patent implements continuous searching operations by maintaining parallel comparison across all word lines throughout the scanning process. Rather than completing one search operation sequentially, the system continuously performs comparisons across multiple word lines simultaneously, ensuring that useful action (data comparison) continues without interruption and maximizing searching efficiency.
Solution Approach 2:
The patent changes the operational parameters by implementing dynamic scanning patterns across word lines and utilizing different comparison strategies (such as bitwise comparison with wild card support). This allows the system to overcome the fixed data width limitation imposed by the number of word lines, effectively increasing the searchable data width through parameter optimization rather than structural change.
3Device complexity
If bit-by-bit comparison is performed for each word line, then the data width can be effectively increased, but the number of operations increases
Solution Approach 1:
The patent performs preliminary actions by pre-loading search data into all word lines before the actual comparison operation begins. This preliminary setup allows subsequent bit-by-bit comparison to proceed efficiently without repeated data loading, reducing the overall time penalty associated with increased operational count.
Solution Approach 2:
The patent implements periodic scanning patterns where comparison operations are performed in systematic cycles across different word lines. This periodic structure allows the system to interleave comparison operations with data preparation and processing, thereby utilizing idle time periods and reducing the total elapsed time despite the increased number of individual operations required for wider data processing.
Data Source
AI summary
A memory device and in-memory searching method are provided. The memory device is, for example, a three dimensional NAND flash memory circuit, and provides a storage media with high-performance and high-capacity. The memory device includes an address scanner, a searching data transmitter, a readout data sensor and comparator, an error bit detector, and a matching status processor. The address scanner provides a scanned address information within a search setting range. The readout data sensor and comparator compares a readout data with a search data bit by bit to generate a comparison result. The error bit detector determines a matching information of the readout data and the search data according to the comparison result. The matching status processor generates a matching address information.