3D NAND Flash Memory Block Segmentation for Voltage Control
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently managing data operations, particularly in writing, reading, and erasing processes due to limitations in voltage application and interconnection delays, which affect the reliability and speed of data storage in three-dimensional NAND flash memory systems.
Innovation Solution
The semiconductor storage device employs a configuration with multiple transistors and control circuits that allow for simultaneous voltage application to memory cells in blocks, utilizing a stacked body structure with alternately stacked conductive and insulating layers, and pillars that extend through the substrate, enabling efficient data operations by optimizing the layout and interconnection of transistors and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are operated simultaneously in blocks, then data operation speed and efficiency are improved, but voltage application control complexity and interconnection delay management become more difficult
Solution Approach 1:
The memory array is divided into multiple blocks, each block containing several memory cells that can be operated independently. This segmentation allows simultaneous operation of multiple blocks while maintaining manageable control complexity within each block. The control circuitry can address each block separately, applying voltages to multiple cells within a block without overwhelming the control system.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked memory structure. Memory cells are arranged in vertical pillars extending through multiple stacked layers, enabling parallel access to cells across different vertical levels. This dimensional change allows simultaneous operation of multiple cells without proportionally increasing interconnection complexity, as cells in the same block can be accessed through shared word lines and bit lines that span multiple vertical levels.
2Quantity of substance
If three-dimensional stacked structure is used, then storage density is improved, but interconnection delays and voltage application limitations increase
Solution Approach 1:
The memory architecture utilizes vertical stacking of multiple memory layers with pillars extending through the stack in the thickness direction. This three-dimensional arrangement dramatically increases storage density by utilizing the vertical dimension. Meanwhile, word lines and bit lines are configured to extend across multiple vertical levels, allowing simultaneous access to cells at different heights within the same block, thereby minimizing interconnection delays despite the increased vertical distance.
Solution Approach 2:
The stacked memory structure is divided into multiple independently controllable blocks. Each block contains a specific set of memory cells accessible through dedicated word lines and bit lines. This segmentation allows the control circuit to manage voltage application to different blocks independently, reducing the overall interconnection delay by limiting the voltage propagation distance within each block while maintaining high storage density through the stacked configuration.
3Productivity
If simultaneous voltage application to multiple memory cells is enabled, then data operation efficiency is improved, but reliability and precision of voltage control decrease
Solution Approach 1:
Memory cells are organized into blocks with dedicated control circuits for each block. The control circuit applies voltages to word lines and bit lines that are isolated to specific blocks, ensuring that voltage application to one block does not interfere with other blocks. This segmentation maintains voltage control precision even when multiple blocks are operated simultaneously, as each block's voltage signals are independently managed.
Solution Approach 2:
The control circuit acts as an intermediary between the external interface and the memory cells, managing voltage application to multiple cells simultaneously. It coordinates the timing and levels of voltages applied to word lines and bit lines within each block, ensuring precise control. The control circuit can selectively activate only the necessary word lines and bit lines for the current operation, reducing voltage interference and maintaining reliability while enabling parallel operations across multiple blocks.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.