3D NAND Stack Layout With Block Separation for Higher Density
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Solution Overview
Problem
Semiconductor devices face challenges in achieving reduced volume and high capacity data processing, necessitating an increase in integration density.
Innovation Solution
The semiconductor device incorporates a substrate with spaced plate portions, stack structures separated by block and cell array separation structures, and channel structures penetrating these stacks, featuring alternating interlayer insulating layers and gate electrodes, to enhance integration density and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar transistor structure is used, then the device structure is simple and easy to manufacture, but the integration density is low
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by stacking multiple layers including semiconductor layers, gate electrodes, and insulating layers vertically. This dimensional change enables significantly higher integration density while maintaining manufacturability through established semiconductor fabrication processes adapted for vertical architectures.
2Quantity of substance
If integration density is increased through vertical stacking, then the device capacity increases, but the separation region waste increases
Solution Approach 1:
The patent divides the vertical stack structure into multiple functional segments separated by insulating layers and spacer structures. These segmented regions allow independent optimization of different device functions while minimizing the space required for separation, thereby reducing separation region waste and improving overall integration density.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers are stacked vertically within a compact footprint. The gate electrodes, semiconductor layers, and insulating layers are arranged in concentric or nested configurations that maximize space utilization and minimize the area required for separation regions between functional blocks.
3Volume of moving object
If vertical stack structures are used to improve integration density, then the device volume is reduced, but the electrical properties may deteriorate
Solution Approach 1:
The patent applies different material compositions and structural configurations to specific regions of the vertical stack to optimize local electrical properties. For example, different semiconductor layers may have different doping concentrations, and gate electrodes may have varying thicknesses or materials in different sections, allowing tailored electrical characteristics throughout the device while maintaining compact volume.
Solution Approach 2:
The patent employs composite material structures combining multiple materials with complementary electrical properties in the vertical stack. This includes combining different dielectric materials for insulating layers, different semiconductor materials for channel regions, and various conductive materials for gate electrodes, thereby optimizing electrical performance within the reduced device volume.
Data Source
AI summary
A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.