3D NAND Memory Bonded Peripheral Circuit Stacking for Smaller Chips
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Solution Overview
Problem
The challenge in developing three-dimensional (3D) memory devices is the increasing complexity and cost of scaling down peripheral circuits while maintaining high voltage requirements, which limits the reduction of chip size and memory density due to the need for more layers and increased metal routing, and the infeasibility of reducing voltage for memory operations like program and erase.
Innovation Solution
The solution involves stacking peripheral circuits in different planes vertically, separating memory cell arrays and peripheral circuits based on voltage requirements, and using hybrid bonding and transfer bonding to reduce fabrication complexity and interconnect costs, allowing for independent thermal budgets and the use of low-thermal-budget materials like copper for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuits are scaled down to reduce chip size, then chip area is reduced, but fabrication complexity and cost increase due to more layers and metal routing
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking, placing memory cell arrays and peripheral circuits in different vertical planes. This dimensional change allows both high-density memory and complex peripheral circuits to coexist without increasing planar chip area, as circuits are routed vertically through interconnect layers between stacked structures.
Solution Approach 2:
The patent segments the chip into multiple functional layers: memory cell array layers and peripheral circuit layers are separated and stacked vertically. This segmentation allows independent optimization of each layer's fabrication process and reduces the complexity burden on any single layer, as each can be designed and manufactured with appropriate complexity levels.
2Use of energy by moving object
If voltage is reduced for memory operations, then power consumption decreases, but high voltage requirements for program and erase operations cannot be met
Solution Approach 1:
The patent implements different voltage levels in different spatial locations: low-voltage peripheral circuits operate at reduced voltages for minimal power consumption, while high-voltage memory cell arrays maintain full voltage capability for program and erase operations. The vertical stacking and separate interconnect structures enable this local voltage differentiation without interference between high and low voltage domains.
3Quantity of substance
If more layers are stacked to increase memory density, then memory capacity increases, but interconnect routing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension for interconnect routing, placing different interconnect layers between stacked memory cell arrays and peripheral circuits. This vertical routing approach consolidates multiple signal paths into structured layers, reducing the planar routing complexity that would otherwise result from connecting numerous memory cells and circuits in a 2D layout.
4Ease of manufacture
If hybrid bonding and transfer bonding are used to reduce fabrication complexity, then manufacturing ease improves, but bonding interface reliability must be maintained
Solution Approach 1:
The patent employs bonding interface layers as intermediaries between stacked semiconductor structures. These specialized interconnect layers facilitate hybrid bonding and transfer bonding processes by providing appropriate surface properties and material compositions, enabling reliable mechanical and electrical bonding while simplifying the overall fabrication process through standardized bonding interfaces.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.